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公开(公告)号:US12048137B2
公开(公告)日:2024-07-23
申请号:US17404260
申请日:2021-08-17
发明人: Po-Sheng Wang , Ru-Yu Wang , Yangsyu Lin , You-Cheng Xiao
IPC分类号: H01L23/00 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786 , H10B10/00
CPC分类号: H10B10/18 , H01L21/0259 , H01L21/823807 , H01L27/0922 , H01L29/0665 , H01L29/42392 , H01L29/66742 , H01L29/78696
摘要: A semiconductor arrangement includes a memory array including bitcells and a peripheral logic block for accessing the bitcells. The peripheral logic block includes a first nanostructure having a first width for providing power to a first logic unit of the peripheral logic block, and a second nanostructure axially aligned with the first nanostructure and having a second width less than the first width for providing power to a second logic unit of the peripheral logic block.
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公开(公告)号:US08923078B2
公开(公告)日:2014-12-30
申请号:US13751240
申请日:2013-01-28
IPC分类号: G11C7/00 , H03K17/284
CPC分类号: H03K17/284 , G11C7/00 , G11C11/417 , H03K17/04123
摘要: One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly.
摘要翻译: 本文提供了用于控制分压器的一种或多种技术或系统。 在一些实施例中,控制电路被配置为使用模拟信号来偏置分压器的上拉单元,从而使分压器能够可调。 换句话说,控制电路使得分压器能够输出多个电压电平。 另外,控制电路被配置为基于与分压器的下拉单元相关联的偏置定时偏压上拉单元。 例如,下拉单元启动后,上拉单元被激活。 以这种方式,控制电路提供定时提升,从而使得分压器能够更快地稳定。
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公开(公告)号:US20140211574A1
公开(公告)日:2014-07-31
申请号:US13751240
申请日:2013-01-28
IPC分类号: H03K17/284 , G11C7/00
CPC分类号: H03K17/284 , G11C7/00 , G11C11/417 , H03K17/04123
摘要: One or more techniques or systems for controlling a voltage divider are provided herein. In some embodiments, a control circuit is configured to bias a pull up unit of a voltage divider using an analog signal, thus enabling the voltage divider to be level tunable. In other words, the control circuit enables the voltage divider to output multiple voltage levels. Additionally, the control circuit is configured to bias the pull up unit based on a bias timing associated with a pull down unit of the voltage divider. For example, the pull up unit is activated after the pull down unit is activated. In this manner, the control circuit provides a timing boost, thus enabling the voltage divider to stabilize more quickly.
摘要翻译: 本文提供了用于控制分压器的一种或多种技术或系统。 在一些实施例中,控制电路被配置为使用模拟信号来偏置分压器的上拉单元,从而使分压器能够可调。 换句话说,控制电路使得分压器能够输出多个电压电平。 另外,控制电路被配置为基于与分压器的下拉单元相关联的偏置定时偏压上拉单元。 例如,下拉单元启动后,上拉单元被激活。 以这种方式,控制电路提供定时提升,从而使得分压器能够更快地稳定。
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公开(公告)号:US20210232168A1
公开(公告)日:2021-07-29
申请号:US16775570
申请日:2020-01-29
发明人: Haruki Mori , Hidehiro Fujiwara , Zhi-Hao Chang , Yangsyu Lin , Yu-Hao Hsu , Yen-Huei Chen , Hung-Jen Liao , Chiting Cheng
IPC分类号: G05F3/24 , H01L23/528 , H01L27/092 , G06F1/28
摘要: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
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公开(公告)号:US10263621B2
公开(公告)日:2019-04-16
申请号:US15468296
申请日:2017-03-24
发明人: Shang-Chi Wu , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号: H03L5/00 , H03K19/00 , H03K19/0185
摘要: A level shifter that comprises an input operating in an input voltage domain and an output for outputting an output signal in an output voltage domain. The level shifter further includes an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal. The level shifter also includes an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal. An output buffer circuit generates the output signal based at least in part on the inverted input signal and the intermediate signal.
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公开(公告)号:US11199866B2
公开(公告)日:2021-12-14
申请号:US16775570
申请日:2020-01-29
发明人: Haruki Mori , Hidehiro Fujiwara , Zhi-Hao Chang , Yangsyu Lin , Yu-Hao Hsu , Yen-Huei Chen , Hung-Jen Liao , Chiting Cheng
IPC分类号: G05F1/10 , G05F3/24 , G06F1/28 , H01L27/092 , H01L23/528
摘要: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.
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公开(公告)号:US20180278252A1
公开(公告)日:2018-09-27
申请号:US15468296
申请日:2017-03-24
发明人: Shang-Chi Wu , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号: H03K19/0185
CPC分类号: H03K19/018521
摘要: A level shifter that comprises an input operating in an input voltage domain and an output for outputting an output signal in an output voltage domain. The level shifter further includes an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal. The level shifter also includes an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal. An output buffer circuit generates the output signal based at least in part on the inverted input signal and the intermediate signal.
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