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公开(公告)号：US20130145083A1
公开(公告)日：2013-06-06
申请号：US13690961
申请日：2012-11-30
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/1433 , G06F21/79
摘要： According to one embodiment, a semiconductor memory device includes a memory which comprises an area accessible from outside and a confidential information area storing confidential information and a set flag. A controller reads the flag from the memory when instructed to erase data in the confidential information area, determines whether the flag is set, erases data in the confidential information area when the flag is clear, and abandons process requested by the data erase instruction when the flag is set. An authenticator uses data in the confidential information area to execute operation for authentication.
摘要翻译： 根据一个实施例，半导体存储器件包括存储器，其包括可从外部访问的区域和存储机密信息的机密信息区域和设置标志。 当指示擦除机密信息区域中的数据时，控制器从存储器读取标志，确定标志是否被置位，当标志清除时，擦除机密信息区域中的数据，并且当数据擦除指令被请求时放弃由数据擦除指令请求的处理 标志设置。 验证者使用机密信息区域中的数据来执行认证操作。
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公开(公告)号：US20070285980A1
公开(公告)日：2007-12-13
申请号：US11737373
申请日：2007-04-19
申请人： Takahiro SHIMIZU , Noboru Shibata
发明人： Takahiro SHIMIZU , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5643
摘要： A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.
摘要翻译： 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。
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公开(公告)号：US20110141811A1
公开(公告)日：2011-06-16
申请号：US13033309
申请日：2011-02-23
申请人： Takahiro Shimizu , Noboru Shibata
发明人： Takahiro Shimizu , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5643
摘要： A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.
摘要翻译： 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。
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公开(公告)号：US07916534B2
公开(公告)日：2011-03-29
申请号：US11737373
申请日：2007-04-19
申请人： Takahiro Shimizu , Noboru Shibata
发明人： Takahiro Shimizu , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5643
摘要： A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.
摘要翻译： 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。
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5.发明授权Semiconductor memory device including a flag for selectively controlling erasing and writing of confidential information area 有权半导体存储器件包括用于选择性地控制机密信息区域的擦除和写入的标志公开(公告)号：US09256525B2
公开(公告)日：2016-02-09
申请号：US13690961
申请日：2012-11-30
CPC分类号： G06F12/0246 , G06F12/1433 , G06F21/79
摘要： A semiconductor memory device includes a memory which comprises a confidential information area storing confidential information and a flag. A controller reads the flag from the memory when instructed to erase or write data in the confidential information area, determines whether the flag is set, erases or writes data in the confidential information area when the flag is clear, and abandons a process requested by an erase or write instruction when the flag is set. An authenticator uses data in the confidential information area to execute an operation for authentication. A management information area may store management information for associated pages. The flag may include a bit string and a complementary bit string to improve reliability of the flag. The confidential information area may store dummy data when the memory is used for uses other than an application with an authentication function, so no problem arises using a normal controller.
摘要翻译： 半导体存储器件包括存储机密信息区域和标志的存储器。 当指示擦除或写入机密信息区中的数据时，控制器从存储器中读取该标志，当该标志清除时，确定在机密信息区中是否设置，擦除或写入数据，并放弃由 设置标志时擦除或写入指令。 验证者使用机密信息区域中的数据来执行认证操作。 管理信息区域可以存储关联页面的管理信息。 标志可以包括位串和互补位串，以提高标志的可靠性。 当存储器被用于除具有认证功能的应用程序之外的使用时，机密信息区域可以存储虚拟数据，因此使用普通控制器不会出现问题。
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公开(公告)号：US08363468B2
公开(公告)日：2013-01-29
申请号：US13033309
申请日：2011-02-23
申请人： Takahiro Shimizu , Noboru Shibata
发明人： Takahiro Shimizu , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5641 , G11C2211/5643
摘要： A semiconductor memory device of the invention comprises a memory cell array which includes a first region that has a plurality of memory cells each capable of storing n-bit data (n is a natural number) and a second region that has a plurality of memory cells each capable of storing k-bit data (k>n: k is a natural number), a data storage circuit which includes a plurality of data caches, and a control circuit which controls the memory cell array and the data storage circuit in such a manner that the k-bit data read from the k/n number of memory cells in the first region are stored into the data storage circuit and the k-bit data are stored into the memory cells in the second region.
摘要翻译： 本发明的半导体存储器件包括存储单元阵列，该存储单元阵列包括具有多个存储单元的第一区域，每个存储器单元能够存储n位数据（n为自然数）和具有多个存储单元的第二区域 每个能够存储k比特数据（k> n：k是自然数），包括多个数据高速缓存的数据存储电路，以及控制该存储单元阵列和数据存储电路的控制电路 将从第一区域中的k / n个存储单元读取的k位数据存储到数据存储电路中的方式，并将k位数据存储到第二区域中的存储单元中。
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公开(公告)号：US08855297B2
公开(公告)日：2014-10-07
申请号：US13524475
申请日：2012-06-15
IPC分类号： G06F21/24
CPC分类号： H04L9/0816 , G11B20/00362 , G11B20/00427 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, an authentication method includes generating, by the memory, first authentication information by calculating secret identification information with a memory session key in one-way function operation, transmitting encrypted secret identification information, a family key block, and the first authentication information to a host, and generating, by the host, second authentication information by calculating the secret identification information generated by decrypting the encrypted secret identification information with the host session key in one-way function operation. The method further includes comparing, by the host, the first authentication information with the second authentication information.
摘要翻译： 根据一个实施例，一种认证方法包括：通过在单向功能操作中用存储器会话密钥计算秘密识别信息，通过存储器生成第一认证信息，发送加密的秘密识别信息，家庭密钥块和第一认证 信息发送到主机，并且由主机通过计算通过用单向功能操作中的主机会话密钥对加密的秘密识别信息进行解密而生成的秘密识别信息来生成第二认证信息。 该方法还包括由主机将第一认证信息与第二认证信息进行比较。
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公开(公告)号：US08812843B2
公开(公告)日：2014-08-19
申请号：US13524843
申请日：2012-06-15
IPC分类号： H04L9/32
CPC分类号： H04L9/0816 , G11B20/00362 , G11B20/00427 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes first and second data generator, a one-way function processor, and a data output interface. The first data generator generates a second key by encrypting a host constant with a first key in AES operation. The second data generator generates a session key by encrypting a random number with a second key in AES operation. The one-way function processor generates authentication information by processing secret identification information with the session key in one-way function operation. The data output interface outputs the encrypted secret identification information, a family key block, and the authentication information to outside of the device.
摘要翻译： 根据一个实施例，设备包括第一和第二数据生成器，单向功能处理器和数据输出接口。 第一个数据生成器通过AES操作中的第一个密钥加密主机常数来生成第二个密钥。 第二数据生成器通过在AES操作中用第二密钥加密随机数生成会话密钥。 单向功能处理器通过在单向功能操作中通过会话密钥处理秘密识别信息来生成认证信息。 数据输出接口将加密的秘密识别信息，家庭密钥块和认证信息输出到设备外部。
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公开(公告)号：US08732466B2
公开(公告)日：2014-05-20
申请号：US13524894
申请日：2012-06-15
IPC分类号： H04L9/32
CPC分类号： H04L9/0816 , G11B20/00086 , G11B20/00115 , G11B20/0021 , G11B2220/2516 , G11B2220/60 , H04L9/0822 , H04L9/0833 , H04L9/0897 , H04L9/32 , H04L2209/601
摘要： According to one embodiment, a device includes a first memory area to store a first key. A second memory area stores encrypted secret identification (ID) information generated from secret ID information with a family key. A third memory area stores a family key block including data generated from the family key with an ID key. An authentication module performs authentication. A second key is generated from a first number with the first key, a session key is generated from a random number with the second key, and authentication information is generated from the secret ID information with the session key. The encrypted secret ID information, family key block and the authentication information is output.
摘要翻译： 根据一个实施例，设备包括用于存储第一密钥的第一存储区域。 第二存储区域存储从秘密ID信息生成的加密的秘密标识（ID）信息与家庭密钥。 第三存储区域存储包括具有ID密钥的家族密钥产生的数据的家庭密钥块。 认证模块执行认证。 从具有第一密钥的第一号码生成第二密钥，从具有第二密钥的随机数生成会话密钥，并且从具有会话密钥的秘密ID信息生成认证信息。 输出加密的秘密ID信息，家庭密钥块和认证信息。
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公开(公告)号：US08687420B2
公开(公告)日：2014-04-01
申请号：US13589842
申请日：2012-08-20
申请人： Noboru Shibata , Kazunori Kanebako
发明人： Noboru Shibata , Kazunori Kanebako
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C29/00 , G11C2211/5642 , G11C2211/5648
摘要： A semiconductor memory device which includes multi-bit memory cells that store multi-bit data and memory cells that store data of fewer bits then that of the multi-bit data. Thus, the semiconductor memory device includes a plurality of memory cells which store n-bit (where n is a natural number that is equal to or larger than 2) data for one cell. Among the plurality of memory cells, h-bit (h≦n) data is stored in a memory MLC of a first region MLB, and i-bit (i
摘要翻译： 一种半导体存储器件，包括存储多位数据的多位存储器单元和存储少位数据以及多位数据的数据的存储器单元。 因此，半导体存储器件包括用于存储一个单元的n位（其中n是等于或大于2的自然数）的多个存储器单元。 在多个存储单元中，h位（h＆nlE; n）数据被存储在第一区域MLB的存储器MLC中，i位（i
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