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    TEST PATTERN GENERATION APPARATUS, TEST PATTERN GENERATION METHOD, AND MEDIUM STORING TEST PATTERN GENERATION PROGRAM
    3.
    发明申请
    TEST PATTERN GENERATION APPARATUS, TEST PATTERN GENERATION METHOD, AND MEDIUM STORING TEST PATTERN GENERATION PROGRAM 审中-公开
    测试图形生成装置，测试图形生成方法和中间存储测试图形生成程序

    公开(公告)号：US20100269076A1

    公开(公告)日：2010-10-21

    申请号：US12696280

    申请日：2010-01-29

    申请人： Fumiyuki Yamane

    发明人： Fumiyuki Yamane

    IPC分类号： G06F17/50

    CPC分类号： G01R31/31813 ,  G01R31/31919

    摘要： A test pattern generation apparatus includes an activation rate setting unit configured to set an activation rate of a cell, a test pattern generator configured to generate a test pattern based on the activation rate set by the activation rate setting unit, a supply voltage calculator configured to calculate a supply voltage of a semiconductor integrated circuit using the test pattern generated by the test pattern generator, and an output unit configured to output the test pattern generated by the test pattern generator when the supply voltage calculated by the supply voltage calculator fulfills the target supply voltage.

    摘要翻译： 一种测试图形生成装置，包括：激活率设定单元，其被配置为设置单元的激活率;测试模式生成器，其被配置为基于由所述激活率设置单元设置的激活率生成测试模式;电源电压计算器，被配置为 使用由测试图案发生器产生的测试图案计算半导体集成电路的电源电压;以及输出单元，其被配置为当由电源电压计算器计算的电源电压满足目标电源时，输出由测试模式发生器产生的测试模式 电压。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US07768334B2

    公开(公告)日：2010-08-03

    申请号：US12264406

    申请日：2008-11-04

    申请人： Fumiyuki Yamane

    发明人： Fumiyuki Yamane

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10

    摘要： A semiconductor integrated circuit has a plurality of clock tree cells arranged in a tree structure on clock signal lines transmitting a clock signal, the plurality of clock tree cells forming a clock tree. The clock tree cells include first power supply lines connected to the clock tree cells, second power supply lines connected to logic circuits receiving a clock signal supplied from the clock tree, and a plurality of power supply pads connected to the first power supply lines and the second power supply lines.

    摘要翻译： 半导体集成电路具有以时钟信号线布置在树形结构中的多个时钟树单元，时钟信号线传输时钟信号，多个时钟树单元形成时钟树。 时钟树单元包括连接到时钟树单元的第一电源线，连接到接收从时钟树提供的时钟信号的逻辑电路的第二电源线以及连接到第一电源线的多个电源焊盘和 第二条电源线。

    DLL circuit
    5.
    发明授权
    DLL circuit 失效
    DLL电路

    公开(公告)号：US07626432B2

    公开(公告)日：2009-12-01

    申请号：US12053937

    申请日：2008-03-24

    申请人： Fumiyuki Yamane

    发明人： Fumiyuki Yamane

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814

    摘要： A DLL circuit has an input circuit configured to generate a synchronization reference signal on the basis of an input signal, a first delay unit configured to delay the synchronization reference signal, a timing offset circuit configured to adjust a synchronization position of the synchronization reference signal delayed by the first delay unit to generate a signal to be synchronized, a phase comparison circuit configured to compare phase of the synchronization reference signal with that of the signal to be synchronized, a first control circuit configured to select an output signal of the first delay unit on the basis of a comparison result of the phase comparison circuit, a second delay unit configured to delay the synchronization reference signal or the signal to be synchronized and a second control circuit configured to select an output signal of the second delay unit in the case where the comparison result of the phase comparison circuit is within a predetermined range. The phase comparison circuit compares the phase of the signal, which is either the synchronization reference signal or the signal to be synchronized, delayed by the second delay unit with the phase of the other signal.

    摘要翻译： DLL电路具有输入电路，其被配置为基于输入信号产生同步参考信号，第一延迟单元被配置为延迟同步参考信号;定时偏移电路，被配置为调整延迟的同步参考信号的同步位置 通过第一延迟单元产生要同步的信号;相位比较电路，被配置为将同步参考信号的相位与要同步的信号的相位进行比较;第一控制电路，被配置为选择第一延迟单元的输出信号 基于相位比较电路的比较结果，第二延迟单元被配置为延迟同步参考信号或要同步的信号，以及第二控制电路，被配置为在第二延迟单元中选择第二延迟单元的输出信号， 相位比较电路的比较结果在预定范围内。 相位比较电路将由第二延迟单元延迟的同步参考信号或同步信号的信号的相位与另一信号的相位进行比较。

    DLL circuit
    6.
    发明授权
    DLL circuit 有权
    DLL电路

    公开(公告)号：US07821313B2

    公开(公告)日：2010-10-26

    申请号：US12475269

    申请日：2009-05-29

    申请人： Fumiyuki Yamane

    发明人： Fumiyuki Yamane

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  H03L7/0805

    摘要： A DLL circuit includes an input circuit generating a synchronization reference signal, a first delay unit delaying the synchronization reference signal to generate a plurality of delayed synchronization reference signals and selecting one of the delayed synchronization reference signals, a timing offset circuit adjusting a synchronization position of the delayed synchronization reference signal to generate a signal to be synchronized, a phase comparison circuit comparing phase of the synchronization reference signal with that of the signal to be synchronized, a first control circuit selecting an output signal of the first delay unit, a second delay unit delaying the synchronization reference signal or the signal to be synchronized to generate a plurality of delayed signals, a configuration information memory storing configuration information, and a second control circuit selecting an output signal of the second delay unit if the comparison result of the phase comparison circuit is within a predetermined range.

    摘要翻译： DLL电路包括产生同步参考信号的输入电路，延迟同步参考信号以产生多个延迟同步参考信号并选择延迟同步参考信号之一的第一延迟单元，调整同步参考信号的同步位置的定时偏移电路 延迟同步参考信号以产生要同步的信号;相位比较电路，比较同步参考信号与待同步信号的相位;选择第一延迟单元的输出信号的第一控制电路;第二延迟 单元延迟同步参考信号或要同步的信号以产生多个延迟信号，配置信息存储器存储配置信息，以及第二控制电路，如果相位比较的比较结果选择第二延迟单元的输出信号 电路与 在预定范围内。

    Static random access memory including potential control means for writing data in memory cell and write method for memory cell
    7.
    发明授权
    Static random access memory including potential control means for writing data in memory cell and write method for memory cell 失效
    静态随机存取存储器包括用于将数据写入存储单元的电位控制装置和用于存储单元的写入方法

    公开(公告)号：US6011713A

    公开(公告)日：2000-01-04

    申请号：US995769

    申请日：1997-12-22

    申请人： Fumiyuki Yamane ,  Tadahiro Kuroda ,  Toshinari Takayanagi ,  Masataka Matsui ,  Yasuo Unekawa ,  Tetsu Nagamatsu

    发明人： Fumiyuki Yamane ,  Tadahiro Kuroda ,  Toshinari Takayanagi ,  Masataka Matsui ,  Yasuo Unekawa ,  Tetsu Nagamatsu

    IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

    CPC分类号： G11C11/419

    摘要： A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data. Since data written in the memory cell suffices to have a potential difference smaller than the potential difference between the power supply potential and the ground potential, the time required to drive the bit line having a large load capacitance is shortened, the power consumption is decreased, and the power consumption necessary for writing data in the memory cell is reduced.

    摘要翻译： 半导体存储器包括：存储单元，包括反相器（IN1，IN2），控制与存储单元连接的接地侧端子（N3）的电位的控制晶体管（T3，T4）;以及控制晶体管T1和T2， 从位线（BL，/ BL）到存储单元的数据。 在写入数据时，控制晶体管将地侧端子（N3）的电位提高到高于接地电位预定电位。 在转移晶体管将具有比位线（BL，/ BL）的电源电位和接地电位之间的电位差的电位差的数据传送到存储单元之后，使存储单元保持数据， 接地侧端子（N3）的电位降低到接地电位以写入数据。 由于写入存储单元的数据足以具有比电源电位和接地电位之间的电位差小的电位差，所以驱动具有大负载电容的位线所需的时间缩短，功耗降低， 并且减少了在存储单元中写入数据所需的功耗。

    Method for designing semiconductor integrated circuit
    8.
    发明授权
    Method for designing semiconductor integrated circuit 有权
    半导体集成电路设计方法

    公开(公告)号：US08060850B2

    公开(公告)日：2011-11-15

    申请号：US12408142

    申请日：2009-03-20

    申请人： Fumiyuki Yamane

    发明人： Fumiyuki Yamane

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5072 ,  G06F2217/78

    摘要： A method for designing a semiconductor integrated circuit, includes: disposing a plurality of cells in a cell layout region on the basis of a net list indicating connection relations of the plurality of cells to satisfy a setup timing condition; generating a plurality of power regions dividing the cell layout region into plurality; calculating a consumption current of each of the power regions by using a cell power file indicating a consumption current of each of the cells; adjusting layout positions of the temporarily disposed cells with reference to the consumption current of each of the power regions in a range that the setup timing condition is not violated; and optimizing hold timing of the cells after the position adjustment of the cells.

    摘要翻译： 一种半导体集成电路的设计方法，包括：基于表示多个单元的连接关系的网表，将多个单元配置在单元布局区域中，以满足设定定时条件; 生成将单元布局区域分割为多个的多个功率区域; 通过使用表示每个单元的消耗电流的单元电力文件来计算每个功率区域的消耗电流; 参照在不违反设定定时条件的范围内的每个功率区域的消耗电流来调整临时配置的单元的布局位置; 并且在单元的位置调整之后优化单元的保持定时。

    DLL circuit
    9.
    发明授权
    DLL circuit 失效
    DLL电路

    公开(公告)号：US07728640B2

    公开(公告)日：2010-06-01

    申请号：US12113612

    申请日：2008-05-01

    申请人： Fumiyuki Yamane

    发明人： Fumiyuki Yamane

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814 ,  H03L7/0802

    摘要： A DLL circuit according to an embodiment of the present invention includes: a delay line configured to output a plurality of delayed signals of a reference signal, the delay line including, a plurality of first delay units connected in series with each other, each of the first delay units being configured to output a delayed signal of the reference signal, a blocking circuit inserted between the first delay units, the blocking circuit being capable of switching between passing and blocking an input delayed signal of the reference signal, and the delay time of the blocking circuit being integer times as large as each of the delay time of the first delay units, and one or more second delay units connected in parallel with the blocking circuit, the same signal as the delayed signal that is input in the blocking circuit being input in the second delay units, each of the second delay units being configured to output a delayed signal of the reference signal, and the delay time of each of the second delay units being equal to the delay time of each of the first delay units; and a blocking control circuit configured to control the blocking circuit whether to pass or block the delayed signal that is input in the blocking circuit.

    摘要翻译： 根据本发明的实施例的DLL电路包括：延迟线，被配置为输出参考信号的多个延迟信号，所述延迟线包括彼此串联连接的多个第一延迟单元， 第一延迟单元被配置为输出参考信号的延迟信号，插入在第一延迟单元之间的阻塞电路，阻塞电路能够在通过和阻塞参考信号的输入延迟信号之间切换，并且延迟时间 阻塞电路是整数倍于第一延迟单元的延迟时间的整数倍，以及与阻塞电路并联连接的一个或多个第二延迟单元，与在阻塞电路中输入的延迟信号相同的信号为 在第二延迟单元中输入，每个第二延迟单元被配置为输出参考信号的延迟信号，并且每个的延迟时间 第二延迟单元等于每个第一延迟单元的延迟时间; 以及阻塞控制电路，被配置为控制所述阻塞电路是否通过或阻塞在所述阻塞电路中输入的延迟信号。