公开(公告)号：US20070002509A1

公开(公告)日：2007-01-04

申请号：US11477720

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： H02H9/00

CPC分类号： G09G3/3688 ,  G02F1/13452 ,  G02F2202/28 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027

摘要： An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

摘要翻译： 集成电路器件包括形成在矩形区域中并与焊盘PDx电连接的焊盘PDx和静电放电保护元件ESDx。 垫PDx设置在静电放电保护元件ESDx的上层中，使得焊盘的布置方向平行于形成有静电放电保护元件ESDx的区域的长边方向，并且焊盘PDx重叠 部分或全部静电放电保护元件ESDx。

公开(公告)号：US20070000971A1

公开(公告)日：2007-01-04

申请号：US11477741

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： A47J36/02

CPC分类号： H01L27/0207 ,  G09G3/3688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116

摘要： An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.

摘要翻译： 集成电路装置包括连接在第一和第二电源线之间的第一和第二晶体管NTr1和PTr1推挽，并通过电荷泵操作将第一和第二电源线之一的电压输出到连接节点ND 以及与连接节点ND电连接并与在一端施加给定电压的飞跨电容器电连接在浮动电容器的另一端的焊盘PD。 焊盘PD设置在第一和第二晶体管NTr 1和PTr 1中的至少一个的上层中，使得焊盘PD与第一和第二晶体管NTr 1和PTr 1中的至少一个晶体管的一部分或全部重叠。

公开(公告)号：US08310478B2

公开(公告)日：2012-11-13

申请号：US11477741

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： G06F3/038

CPC分类号： H01L27/0207 ,  G09G3/3688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116

摘要： An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.

摘要翻译： 集成电路装置包括连接在第一和第二电源线之间的第一和第二晶体管NTr1和PTr1推挽，并通过电荷泵操作将第一和第二电源线之一的电压输出到连接节点ND，以及 与连接节点ND电连接并与在一端施加给定电压的飞跨电容器电连接在浮动电容器的另一端处的焊盘PD。 焊盘PD设置在第一和第二晶体管NTr1和PTr1中的至少一个的上层中，使得焊盘PD与第一和第二晶体管NTr1和PTr1中的至少一个晶体管的一部分或全部重叠。

公开(公告)号：US08188544B2

公开(公告)日：2012-05-29

申请号：US11477720

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： H01L23/62

CPC分类号： G09G3/3688 ,  G02F1/13452 ,  G02F2202/28 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027

摘要： An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.

摘要翻译： 集成电路器件包括形成在矩形区域中并与焊盘PDx电连接的焊盘PDx和静电放电保护元件ESDx。 垫PDx设置在静电放电保护元件ESDx的上层中，使得焊盘的布置方向平行于形成有静电放电保护元件ESDx的区域的长边方向，并且焊盘PDx重叠 部分或全部静电放电保护元件ESDx。

公开(公告)号：US20110128274A1

公开(公告)日：2011-06-02

申请号：US13022995

申请日：2011-02-08

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru ITO ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru ITO ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Takayuki Saiki ,  Hiroyuki Takamiya

IPC分类号： G06F3/038

CPC分类号： H01L27/0207 ,  G09G3/3688 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1116

摘要： An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.

摘要翻译： 集成电路装置包括连接在第一和第二电源线之间的第一和第二晶体管NTr1和PTr1推挽，并通过电荷泵操作将第一和第二电源线之一的电压输出到连接节点ND，以及 与连接节点ND电连接并与在一端施加给定电压的飞跨电容器电连接在浮动电容器的另一端处的焊盘PD。 焊盘PD设置在第一和第二晶体管NTr1和PTr1中的至少一个的上层中，使得焊盘PD与第一和第二晶体管NTr1和PTr1中的至少一个晶体管的一部分或全部重叠。

公开(公告)号：US08547773B2

公开(公告)日：2013-10-01

申请号：US11477714

申请日：2006-06-30

申请人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

发明人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

IPC分类号： G11C8/00

CPC分类号： G09G3/3674 ,  G09G3/3685

摘要： An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.

摘要翻译： 集成电路装置包括用于驱动数据线的至少一个数据驱动器块，多个控制晶体管TC1和TC2，每个控制晶体管对应于数据驱动器模块的每个输出线提供，并通过使用公共控制信号 以及其中设置用于电连接数据线和数据驱动器块的输出线QL1和QL2的数据驱动器焊盘P1和P2的焊盘布置区域。 控制晶体管TC1和TC2设置在焊盘布置区域中。

公开(公告)号：US20070013634A1

公开(公告)日：2007-01-18

申请号：US11477714

申请日：2006-06-30

申请人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

发明人： Takayuki Saiki ,  Satoru Ito ,  Masahiko Moriguchi ,  Takashi Kumagai ,  Hisanobu Ishiyama ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira ,  Kazuhiro Maekawa

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G3/3685

摘要： An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled. by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.

摘要翻译： 集成电路装置包括用于驱动数据线的至少一个数据驱动器块，多个控制晶体管TC 1和TC 2，每个控制晶体管被提供对应于数据驱动器模块的每个输出线并被控制。 以及用于电连接数据驱动器块的数据线和输出线QL 1和QL 2的数据驱动器焊盘P 1和P 2的焊盘布置区域。 控制晶体管TC 1和TC 2设置在焊盘布置区域中。

公开(公告)号：US07522441B2

公开(公告)日：2009-04-21

申请号：US11270553

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

IPC分类号： G11C5/06

CPC分类号： G09G3/2096 ,  G09G3/3666 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2360/18

摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2≦M≦N−1) of the circuit blocks CB1 to CBN.

摘要翻译： 一种集成电路装置，包括沿着第一方向D1设置的第一至第N电路块CB1至CBN，当第一方向D1是从集成电路器件的第一侧朝向与第一侧相反的第三侧的方向时， 第一侧为短边，当第二方向D2为从集成电路器件的第二侧向与第二侧相反的第四侧的方向时，第二侧为长边。 电路块CB1至CBN包括通过使用差分信号的串行总线传送数据的高速接口电路块HB以及HB以外的电路块。 高速接口电路块HB被布置为电路块CB1至CBN的第M个电路块CBM（2 <= M <= N-1）。

公开(公告)号：US20070002188A1

公开(公告)日：2007-01-04

申请号：US11477715

申请日：2006-06-30

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

IPC分类号： G02F1/00 ,  H04N5/74

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/2096 ,  G09G3/3648 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027 ,  G09G2310/0278 ,  G09G2310/0289 ,  G09G2320/0285 ,  G09G2320/0673 ,  G09G2330/028 ,  G09G2330/04 ,  G09G2360/18

摘要： An integrated circuit device includes first to Nth circuit blocks CB1 to CBN disposed along a direction D1 when a direction from a first side which is a short side of the integrated circuit device toward a third side opposite to the first side is a direction D1 and a direction from a second side which is a long side of the integrated circuit device toward a fourth side opposite to the second side is a direction D2. At least one of the circuit blocks on both ends of the circuit blocks CB1 to CBN is a scan driver block for driving a scan line. Or, the scan driver block SB is disposed along the direction D1 on the side of the first to Nth circuit blocks in the direction D2.

摘要翻译： 集成电路器件包括沿着方向D1设置的第一至第N电路块CB 1至CB N，当从集成电路器件的短边的第一侧朝向与第一侧相反的第三侧的方向为方向D时 1和从集成电路装置的长边朝向与第二侧相反的第四侧的第二侧的方向是方向D 2.电路块CB 1至第二侧的至少一个电路块 CBN是用于驱动扫描线的扫描驱动器块。 或者，扫描驱动块SB沿方向D 1沿方向D 2在第一至第N电路块侧设置。

公开(公告)号：US20070002061A1

公开(公告)日：2007-01-04

申请号：US11270553

申请日：2005-11-10

申请人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

发明人： Takashi Kumagai ,  Hisanobu Ishiyama ,  Kazuhiro Maekawa ,  Satoru Ito ,  Takashi Fujise ,  Junichi Karasawa ,  Satoru Kodaira

IPC分类号： G06F13/14

CPC分类号： G09G3/2096 ,  G09G3/3666 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2310/0289 ,  G09G2310/0297 ,  G09G2360/18

摘要： An integrated circuit device including first to Nth circuit blocks CB1 to CBN disposed along a first direction D1, when the first direction D1 is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D2 is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB1 to CBN include a high-speed interface circuit block HB which transfers data through a serial bus using differential signals, and a circuit block other than HB. The high-speed interface circuit block HB is disposed as an Mth circuit block CBM (2≦M≦N−1) of the circuit blocks CB1 to CBN.

摘要翻译： 一种集成电路装置，包括沿着第一方向D 1布置的第一至第N电路块CB 1至CBN，当第一方向D 1是从集成电路器件的第一侧朝向与第一方向相反的第三侧的方向时 所述第一侧为短边，当第二方向D 2为从所述集成电路器件的第二侧朝向与所述第二侧相反的第四侧的方向时，所述第二侧为长边。 电路块CB 1至CBN包括通过使用差分信号的串行总线传送数据的高速接口电路块HB以及HB以外的电路块。 高速接口电路块HB被布置为电路块CB 1至CBN的第M个电路块CBM（2 <= M <= N-1）。