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1.发明授权公开(公告)号：US06906384B2
公开(公告)日：2005-06-14
申请号：US10096655
申请日：2002-03-14
申请人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
发明人： Takashi Yamada , Tsutomu Sato , Shinichi Nitta , Hajime Nagano , Ichiro Mizushima , Hisato Oyamatsu , Yoshihiro Minami , Shinji Miyano , Osamu Fujii
IPC分类号： H01L21/76 , H01L21/762 , H01L21/764 , H01L21/8234 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/10 , H01L27/108 , H01L27/12 , H01L29/786 , H01L27/01
CPC分类号： H01L27/10861 , H01L21/76243 , H01L21/823481 , H01L21/84 , H01L27/10873 , H01L27/10894 , H01L27/1203 , H01L29/78639
摘要： A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.
摘要翻译： 半导体器件包括第一和第二半导体层以及第一和第二MOS晶体管。 第一半导体层设置在半导体衬底上并与之电连接。 第二半导体层设置在第一半导体层附近，并且经由绝缘膜和空腔中的一个形成在半导体基板的上方。 第一和第二MOS晶体管分别设置在第一和第二半导体层上，并且各自具有平行于第一和第二半导体层之间的边界排列的栅电极。
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2.发明授权Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions 失效组合体积和SOI区域并与多个隔离区域分开的半导体芯片公开(公告)号：US07148543B2
公开(公告)日：2006-12-12
申请号：US10828337
申请日：2004-04-21
申请人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
发明人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/10832 , H01L27/10861 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
摘要翻译： 半导体芯片包括基底基板，在基底基板的一部分上具有体积生长层的体器件区域，在基底基板上具有埋入绝缘体的SOI器件区域和埋入绝缘体上的硅层，以及边界层 位于体器件区域和SOI器件区域之间的边界处。 本体装置区域具有第一装置制造表面，其中大块装置位于本体生长层上。 SOI器件区域具有第二器件制造表面，其中SOI器件位于硅层上。 第一和第二装置制造表面被定位在基本均匀的水平。
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公开(公告)号：US07018904B2
公开(公告)日：2006-03-28
申请号：US10921273
申请日：2004-08-19
申请人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
发明人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/10832 , H01L27/10861 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
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4.发明申请Semiconductor chip having multiple functional blocks integrated in a single chip and method for fabricating the same 失效具有集成在单个芯片中的多个功能块的半导体芯片及其制造方法公开(公告)号：US20050019999A1
公开(公告)日：2005-01-27
申请号：US10921273
申请日：2004-08-19
申请人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
发明人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/8242 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/108 , H01L27/12 , H01L21/336 , H01L21/76 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/10832 , H01L27/10861 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
摘要翻译： 半导体芯片包括基底基板，在基底基板的一部分上具有体积生长层的体器件区域，在基底基板上具有掩埋绝缘体的SOI器件区域和埋入绝缘体上的硅层，以及边界层 位于体器件区域和SOI器件区域之间的边界处。 本体装置区域具有第一装置制造表面，其中大块装置位于本体生长层上。 SOI器件区域具有第二器件制造表面，其中SOI器件位于硅层上。 第一和第二装置制造表面被定位在基本均匀的水平。
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5.发明授权Semiconductor chip which combines bulk and SOI regions and separates same with plural isolation regions 失效组合体积和SOI区域并与多个隔离区域分开的半导体芯片公开(公告)号：US06835981B2
公开(公告)日：2004-12-28
申请号：US09995594
申请日：2001-11-29
申请人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
发明人： Takashi Yamada , Hajime Nagano , Ichiro Mizushima , Tsutomu Sato , Hisato Oyamatsu , Shinichi Nitta
IPC分类号： H01L2701
CPC分类号： H01L27/10894 , H01L21/76264 , H01L21/76283 , H01L21/84 , H01L27/10832 , H01L27/10861 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.
摘要翻译： 半导体芯片包括基底基板，在基底基板的一部分上具有体积生长层的体器件区域，在基底基板上具有掩埋绝缘体的SOI器件区域和埋入绝缘体上的硅层，以及边界层 位于体器件区域和SOI器件区域之间的边界处。 本体装置区域具有第一装置制造表面，其中大块装置位于本体生长层上。 SOI器件区域具有第二器件制造表面，其中SOI器件位于硅层上。 第一和第二装置制造表面被定位在基本均匀的水平。
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6.发明授权Semiconductor device comprising multiple layers with trenches formed on a semiconductor substrate 有权半导体器件包括形成在半导体衬底上的具有沟槽的多层公开(公告)号：US07187035B2
公开(公告)日：2007-03-06
申请号：US10237206
申请日：2002-09-09
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.
摘要翻译： 公开了一种制造半导体器件衬底的方法，其包括通过电绝缘层形成在半导体层与半导体衬底的表面绝缘的图案化的掩模层，根据掩模层的图案蚀刻半导体层以形成 导通绝缘层的沟槽，蚀刻比半导体衬底更薄的保护层比绝缘层的厚度形成覆盖沟槽侧表面的侧壁保护膜，从绝缘层的底表面蚀刻绝缘层 沟槽到半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。
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7.发明申请Semiconductor device substrate and method of manufacturing semiconductor device substrate 失效半导体器件基板和半导体器件基板的制造方法公开(公告)号：US20060234478A1
公开(公告)日：2006-10-19
申请号：US11455735
申请日：2006-06-20
IPC分类号： H01L21/36
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer on the semiconductor substrate having a thickness less than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.
摘要翻译： 一种制造半导体器件基板的方法包括：通过电绝缘层在与半导体衬底的表面绝缘的半导体层上形成掩模层图案，根据掩模层的图案蚀刻半导体层，形成通向 绝缘层，蚀刻具有小于绝缘层厚度的厚度的半导体衬底上的保护层，以形成覆盖沟槽侧表面的侧壁保护膜，从沟槽的底表面蚀刻绝缘层至 半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。
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8.发明授权公开(公告)号：US07521300B2
公开(公告)日：2009-04-21
申请号：US11455735
申请日：2006-06-20
IPC分类号： H01L21/762
CPC分类号： H01L27/1203 , H01L21/84
摘要： A method of manufacturing a semiconductor device substrate includes forming a mask layer pattern on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer on the semiconductor substrate having a thickness less than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.
摘要翻译： 一种制造半导体器件基板的方法包括：通过电绝缘层在与半导体衬底的表面绝缘的半导体层上形成掩模层图案，根据掩模层的图案蚀刻半导体层，形成通向 绝缘层，蚀刻具有小于绝缘层厚度的厚度的半导体衬底上的保护层，以形成覆盖沟槽侧表面的侧壁保护膜，从沟槽的底表面蚀刻绝缘层至 半导体衬底; 以及从蚀刻绝缘层而暴露的半导体衬底的表面生长单晶层。
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9.发明授权Semiconductor device formed in semiconductor layer arranged on substrate with one of insulating film and cavity interposed between the substrate and the semiconductor layer 失效在半导体层中形成的半导体器件，其布置在基板上，绝缘膜和空腔中的一个介于基板和半导体层之间公开(公告)号：US07420249B2
公开(公告)日：2008-09-02
申请号：US11849682
申请日：2007-09-04
申请人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
发明人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/764 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/10897 , H01L27/1203 , H01L27/1207
摘要： A semiconductor device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer surrounding the first semiconductor layer, the second semiconductor layer being formed on the semiconductor substrate with one of an insulating film and a cavity, and a third semiconductor layer surrounding the second semiconductor layer, the third semiconductor layer being formed on the semiconductor substrate.
摘要翻译： 一种半导体器件，包括形成在半导体衬底上的第一半导体层，围绕第一半导体层的第二半导体层，在半导体衬底上形成有绝缘膜和空腔中的一个的第二半导体层和围绕 所述第二半导体层，所述第三半导体层形成在所述半导体衬底上。
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公开(公告)号：US07019365B2
公开(公告)日：2006-03-28
申请号：US10637665
申请日：2003-08-11
申请人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
发明人： Tsutomu Sato , Hajime Nagano , Ichiro Mizushima , Takashi Yamada , Yuso Udo , Shinichi Nitta
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/764 , H01L21/76264 , H01L21/76283 , H01L21/76289 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/10897 , H01L27/1203 , H01L27/1207
摘要： A semiconductor device according to an aspect of the present invention comprises a first semiconductor layer and a plurality of second semiconductor layers. The first semiconductor layer is formed in a first region of a semiconductor substrate with one of an insulating film and a cavity interposed between the semiconductor substrate and the first semiconductor layer. The plurality of second semiconductor layers is formed in second regions of the semiconductor substrate.
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