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公开(公告)号：US20070180006A1
公开(公告)日：2007-08-02
申请号：US11698188
申请日：2007-01-26
IPC分类号： G06F15/00
CPC分类号： G06F13/1652 , G11C7/1006 , Y02D10/14
摘要： In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.
摘要翻译： 在并行运算处理装置中，具有布置在各自具有排列成行和列的多个存储单元的存储块之间的运算处理单元，各存储块的各列交替地与存储器的相对侧的运算处理单元连接 块。 通过在一个存储器块中选择一个字线，可以将数据传输到两个操作处理单元。 每个操作处理单元选择的字线数减少，功耗降低。 操作处理单元的位操作单元和读出放大器/写驱动器具有减轻的布置节距条件，并且数量减少，并且不需要存储器块之间的隔离区域，并且布局面积减小。 因此，具有布局面积和功耗降低的并行运算处理装置可以实现快速运行。
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公开(公告)号：US07505352B2
公开(公告)日：2009-03-17
申请号：US11698188
申请日：2007-01-26
CPC分类号： G06F13/1652 , G11C7/1006 , Y02D10/14
摘要： In a parallel operational processing device having an operational processing unit arranged between memory blocks each having a plurality of memory cells arranged in rows and columns, the respective columns of each memory block are alternately connected to the operational processing units on the opposite sides of the memory block. By selecting one word line in one memory block, data can be transferred to two operational processing units. The number of the word lines selected per one operational processing unit is reduced, and power consumption is reduced. The bit operation units and sense amplifiers/write drivers of the operational processing units have arrangement pitch conditions mitigated and are reduced in number, and an isolation region between the memory blocks is not required and the layout area is reduced. Thus, the parallel operational processing device with a layout area and the power consumption reduced, can achieve a fast operation.
摘要翻译： 在并行运算处理装置中，具有布置在各自具有排列成行和列的多个存储单元的存储块之间的运算处理单元，各存储块的各列交替地与存储器的相对侧的运算处理单元连接 块。 通过在一个存储器块中选择一个字线，可以将数据传输到两个操作处理单元。 每个操作处理单元选择的字线数减少，功耗降低。 操作处理单元的位操作单元和读出放大器/写驱动器具有减轻的布置节距条件，并且数量减少，并且不需要存储器块之间的隔离区域，并且布局面积减小。 因此，具有布局面积和功耗降低的并行运算处理装置可以实现快速运行。
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公开(公告)号：US07007215B2
公开(公告)日：2006-02-28
申请号：US10173266
申请日：2002-06-18
IPC分类号： G01R31/30
CPC分类号： G11C29/56012 , G01R31/318572 , G01R31/31858 , G11C29/56
摘要： A test signal applied to an embedded memory is changed in synchronization with a test clock signal, set to an invalidated state by an asynchronous control signal asynchronous to the test clock signal and then is applied to a memory. The memory takes in a received signal in synchronization with a memory clock signal. An invalid data generating circuit modifies the test signal in accordance with the asynchronous control signal and generates a test signal and to apply the test signal to the memory. A period of an invalid state of the modified test signal can be adjusted and therefore, by monitoring a changing timing of the asynchronous control signal PTX with an external tester, setup and hold times of a signal for the memory can be measured. Setup and hold times and an access time for an embedded memory can be correctly measured.
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公开(公告)号：US06762967B2
公开(公告)日：2004-07-13
申请号：US10443775
申请日：2003-05-23
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译： 半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。 当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。 当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。 因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。
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公开(公告)号：US06295238B1
公开(公告)日：2001-09-25
申请号：US09604007
申请日：2000-06-26
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C700
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译： 半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。 当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。 当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。 因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。
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公开(公告)号：US06614713B2
公开(公告)日：2003-09-02
申请号：US09922670
申请日：2001-08-07
申请人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
发明人： Tetsushi Tanizaki , Katsumi Dosaka , Mikio Asakura
IPC分类号： G11C800
CPC分类号： G11C29/48 , G11C11/406
摘要： A semiconductor memory device includes a command decoder receiving an external signal and issuing a command, a clock buffer receiving an external clock, gates and a refresh counter. When a test signal is at L-level, an auto-refresh signal is issued in accordance with the output of the command decoder. When the test signal is at H-level, the auto-refresh signal is issued in accordance with the output (external clock) of the clock buffer. Thereby, the test can be performed with a good timing accuracy even by a low-speed tester.
摘要翻译： 半导体存储器件包括命令解码器，接收外部信号并发出命令，时钟缓冲器接收外部时钟，门和刷新计数器。 当测试信号处于L电平时，根据命令解码器的输出发出自动刷新信号。 当测试信号为H电平时，根据时钟缓冲器的输出（外部时钟）发出自动刷新信号。 因此，即使通过低速测试仪，也可以以良好的定时精度进行测试。
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7.发明授权Circuit for reducing test time and semiconductor memory device including the circuit 有权降低测试时间的电路和包括电路的半导体存储器件公开(公告)号：US06779139B2
公开(公告)日：2004-08-17
申请号：US09845494
申请日：2001-05-01
IPC分类号： G11C2900
CPC分类号： G11C29/44 , G01R31/318566 , G11C29/38
摘要： A semiconductor memory device includes: a determination section; an expected value control section; and an accumulation section. The determination section determines coincidence/non-coincidence between input data and an expected value. The expected value control section catches a read expected value in a read operation only. The accumulation section catches a determination result according to an accumulation-transmission signal. When the accumulation-transmission signal is in a transmission state, a determination result is caught, while when the accumulation-transmission signal enters an accumulation state, the next determination result is caught in a case of coincidence determination and once a non-coincidence determination result is caught, thereafter the non-coincidence determination result continues to be held.
摘要翻译： 半导体存储器件包括：确定部分; 预期价值控制部分; 和积累部分。 确定部分确定输入数据与期望值之间的一致/不一致。 期望值控制部分仅在读取操作中捕获读取期望值。 累积部根据累积发送信号来取得判定结果。 当累积发送信号处于发送状态时，判断结果被捕获，而当累计发送信号进入累加状态时，在一致判断的情况下，下一个确定结果被捕获，并且一旦不一致确定结果 被捕获，此后不合格确定结果继续保持。
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公开(公告)号：US20060285576A1
公开(公告)日：2006-12-21
申请号：US11452317
申请日：2006-06-14
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。
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公开(公告)号：US20090058543A1
公开(公告)日：2009-03-05
申请号：US12289230
申请日：2008-10-23
IPC分类号： G01K7/00
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。
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公开(公告)号：US07459983B2
公开(公告)日：2008-12-02
申请号：US11452317
申请日：2006-06-14
IPC分类号： G01K7/00
CPC分类号： G01K7/01
摘要： There is provided a technique which is capable of detecting a temperature of a semiconductor device with high precision. A temperature detection circuit detecting a temperature of a semiconductor device includes a first short-cycle oscillator generating a first clock signal having positive temperature characteristics with respect to a frequency, a second short-cycle oscillator generating a second clock signal having negative temperature characteristics with respect to the frequency, and a temperature signal generation unit generating a temperature signal which is varied according to the temperature of the semiconductor device based on the first and second clock signals.
摘要翻译： 提供了能够高精度地检测半导体器件的温度的技术。 检测半导体器件的温度的温度检测电路包括：第一短周期振荡器，其产生相对于频率具有正温度特性的第一时钟信号;第二短周期振荡器，产生具有负温度特性的第二时钟信号 以及温度信号生成单元，其基于第一和第二时钟信号产生根据半导体器件的温度而变化的温度信号。
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