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    Semiconductor device including chip with complementary I/O cells
    1.
    发明授权
    Semiconductor device including chip with complementary I/O cells 有权
    半导体器件包括具有互补I / O单元的芯片

    公开(公告)号：US08581302B2

    公开(公告)日：2013-11-12

    申请号：US13295053

    申请日：2011-11-12

    申请人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    发明人： Mitsuya Kinoshita ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    IPC分类号： H01L27/118

    CPC分类号： H01L27/0207 ,  H01L24/02 ,  H01L27/11898 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014

    摘要： Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

    摘要翻译： 从具有并行驱动器配置的I / O缓冲器输出的信号稳定可靠性提高。 每个I / O单元具有互补I / O单元，其输出一个输出信号作为由非反相信号和反相信号组成的互补信号。 两个I / O单元并联耦合。 第一反相器的输出部分通过第一布线耦合在一起; 并且第二反相器的输出部分通过第二布线耦合在一起。 第一布线形成在I / O单元的下侧，使得它跨越两个I / O单元，并且第二布线形成在第一布线之上，使得它跨越两个I / O单元。 布置布线使得第一布线的布线长度和第二布线的布线长度基本相等。

    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120126403A1

    公开(公告)日：2012-05-24

    申请号：US13295053

    申请日：2011-11-12

    申请人： Mitsuya KINOSHITA ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    发明人： Mitsuya KINOSHITA ,  Motoo Suwa ,  Akinobu Watanabe ,  Shigezumi Matsui

    IPC分类号： H01L23/498

    CPC分类号： H01L27/0207 ,  H01L24/02 ,  H01L27/11898 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/14131 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014

    摘要： Signals outputted from an I/O buffer with a parallel drive configuration are stabilized for reliability enhancement. Each I/O cell has a complementary I/O cell that outputs one output signal as a complementary signal made up of a non-inverted signal and an inverted signal. Two I/O cells are coupled in parallel. Output portions of first inverters are coupled together through a first wiring; and output portions of second inverters are coupled together through a second wiring. The first wiring is formed on the lower side of the I/O cells so that it is astride the two I/O cells, and the second wiring is formed above the first wiring so that it is astride the two I/O cells. The wirings are laid out so that the wiring length of the first wiring and the wiring length of the second wiring are substantially equal to each other.

    摘要翻译： 从具有并行驱动器配置的I / O缓冲器输出的信号稳定可靠性提高。 每个I / O单元具有互补I / O单元，其输出一个输出信号作为由非反相信号和反相信号组成的互补信号。 两个I / O单元并联耦合。 第一反相器的输出部分通过第一布线耦合在一起; 并且第二反相器的输出部分通过第二布线耦合在一起。 第一布线形成在I / O单元的下侧，使得它跨越两个I / O单元，并且第二布线形成在第一布线之上，使得它跨越两个I / O单元。 布置布线使得第一布线的布线长度和第二布线的布线长度基本相等。

    Voltage generation circuit capable of supplying stable power supply voltage to load operating in response to timing signal
    4.
    发明授权
    Voltage generation circuit capable of supplying stable power supply voltage to load operating in response to timing signal 失效
    电压产生电路能够提供稳定的电源电压以响应于定时信号而工作

    公开(公告)号：US6084386A

    公开(公告)日：2000-07-04

    申请号：US362665

    申请日：1999-07-29

    申请人： Mitsue Takahashi ,  Tadaaki Yamauchi ,  Mitsuya Kinoshita

    发明人： Mitsue Takahashi ,  Tadaaki Yamauchi ,  Mitsuya Kinoshita

    IPC分类号： G11C11/413 ,  G05F1/565 ,  G11C11/407 ,  H02M3/137 ,  G05F1/40 ,  G05F1/56

    CPC分类号： G05F1/565

    摘要： A voltage generation circuit includes a voltage comparing circuit to compare a reference voltage signal Vi and an internal power supply voltage Vcc and a current supply transistor to supply current based on the output voltage of the voltage comparing circuit and maintain Vcc. The voltage generation circuit also includes a reference voltage signal generation circuit which responds to a control signal ACT activated for a prescribed time period prior to the operation timing of a load and sets Vi=Vref when control signal ACT is inactive and Vi=Vref+.DELTA.V when control signal ACT is active.

    摘要翻译： 电压产生电路包括用于比较参考电压信号Vi和内部电源电压Vcc的电压比较电路和电流源晶体管，以基于电压比较电路的输出电压提供电流并维持Vcc。 电压产生电路还包括参考电压信号产生电路，其响应于在负载的操作定时之前的规定时间段内激活的控制信号ACT，并且当控制信号ACT无效时设置Vi = Vref，并且Vi = Vref + DELTA V 当控制信号ACT有效时。

    Semiconductor device having no through current flow in standby period
    5.
    发明授权
    Semiconductor device having no through current flow in standby period 失效
    半导体器件在待机期间没有通过电流流动

    公开(公告)号：US5321654A

    公开(公告)日：1994-06-14

    申请号：US863975

    申请日：1992-04-06

    申请人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    发明人： Hiroshi Miyamoto ,  Yoshikazu Morooka ,  Shigeru Mori ,  Shigeru Kikuda ,  Makoto Suwa ,  Mitsuya Kinoshita

    IPC分类号： G11C11/408 ,  G11C5/14 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C11/409 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G11C7/00

    CPC分类号： G11C7/22 ,  G11C5/14 ,  G11C8/18

    摘要： A semiconductor device having amplifying circuits provided near corresponding bonding pads receiving external signals, and positioned between the bonding pads and internal circuits to which such external signals are to be applied. The device includes a control signal generating circuit for the amplifying circuits which is not provided in conventional semiconductor devices. In response to external control signals, the control signal generating circuit generates internal control signals for controlling electric paths between a power supply and ground in the amplifying circuits. During the standby period of the semiconductor device, the paths between the power supply and ground are cut regardless of the potential of the corresponding bonding pads, preventing flow of a through current.

    摘要翻译： 一种具有放大电路的半导体器件，该放大电路设置在相应的接合焊盘附近，接收外部信号，并且位于接合焊盘和要施加这样的外部信号的内部电路之间。 该装置包括用于放大电路的控制信号发生电路，其不在常规半导体器件中提供。 响应于外部控制信号，控制信号发生电路产生用于控制放大电路中的电源和接地之间的电气路径的内部控制信号。 在半导体器件的待机期间，电源和接地之间的路径被切断，而不管相应的焊盘的电位如何，防止通过电流的流动。

    Method for producing a semiconductor integrated circuit device in which circuit functions can be remedied or changed
    6.
    发明授权
    Method for producing a semiconductor integrated circuit device in which circuit functions can be remedied or changed 失效
    制造可补救或改变电路功能的半导体集成电路器件的方法

    公开(公告)号：US5279984A

    公开(公告)日：1994-01-18

    申请号：US45161

    申请日：1993-04-12

    申请人： Mitsuya Kinoshita ,  Kazutami Arimoto ,  Kiyohiro Furutani

    发明人： Mitsuya Kinoshita ,  Kazutami Arimoto ,  Kiyohiro Furutani

    IPC分类号： H01L21/768 ,  H01L23/525 ,  H01L27/118 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L21/76894 ,  H01L23/5258 ,  H01L27/118 ,  H01L2924/0002

    摘要： A semiconductor integrated circuit device in which circuit functions can be remedied or changed by severing at least a portion of a circuit pattern and a method for producing such semiconductor integrated circuit device. The circuit pattern is formed on the semiconductor substrate. A field shield plate is formed on the major surface of the semiconductor substrate for electrically separating respective elements constituting the circuit. The circuit pattern includes a fuse element. The fuse element is provided on the field shield plate. The portion of the field shield plate lying directly below the fuse element is isolated from other portions of the field shield plate. In such semiconductor integrated circuit device, the portion of the field shield plate lying directly below the fuse element is separated from other portions of the field shield plate, so that short-circuiting between the semiconductor substrate and the field shield plate cannot occur even when the laser beam is irradiated with a laser beam deviation at the time of severing of the fuse element.

    摘要翻译： 一种半导体集成电路器件，其中可以通过切断电路图案的至少一部分来补救或改变电路功能，以及用于制造这种半导体集成电路器件的方法。 电路图案形成在半导体衬底上。 在半导体基板的主表面上形成场屏蔽板，用于电分离构成电路的各个元件。 电路图案包括熔丝元件。 保险丝元件设置在场屏蔽板上。 位于保险丝元件正下方的场屏蔽板的部分与场屏蔽板的其它部分隔离。 在这样的半导体集成电路器件中，位于熔丝元件正下方的场屏蔽板的部分与场屏蔽板的其他部分分离，使得半导体衬底和场屏蔽板之间的短路即使在 激光束在熔断元件断开时被激光束的偏离照射。

    Associative memory having simplified memory cell circuitry
    7.
    发明授权
    Associative memory having simplified memory cell circuitry 失效
    具有简化的存储单元电路的关联存储器

    公开(公告)号：US4965767A

    公开(公告)日：1990-10-23

    申请号：US380428

    申请日：1989-07-17

    申请人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

    发明人： Mitsuya Kinoshita ,  Masaaki Mihara ,  Toshifumi Kobayashi ,  Takeshi Hamamoto

    IPC分类号： G11C15/04

    CPC分类号： G11C15/043 ,  G11C15/04

    摘要： A memory cell circuit of an associative memory composed of only four NMOS transistors is disclosed. Each memory cells of the circuit is connected two bit lines, a word line, a match setup line for commanding coincidence detection, and a match line for transferring the results of detection. The data signals are stored in the gate capacity of each of the transistors 3. This simplified memory cell circuit contributes to higher integration of the associative memory.

    摘要翻译： 公开了仅由四个NMOS晶体管组成的相关存储器的存储单元电路。 电路的每个存储单元连接两个位线，字线，用于命令一致检测的匹配设置线和用于传送检测结果的匹配线。 数据信号以每个晶体管3的栅极容量存储。这种简化的存储单元电路有助于关联存储器的更高的集成。

    Semiconductor memory device having self-precharge function
    9.
    发明授权
    Semiconductor memory device having self-precharge function 失效
    具有自放电功能的半导体存储器件

    公开(公告)号：US06930950B2

    公开(公告)日：2005-08-16

    申请号：US10706964

    申请日：2003-11-14

    申请人： Mitsuya Kinoshita ,  Hideyuki Noda

    发明人： Mitsuya Kinoshita ,  Hideyuki Noda

    IPC分类号： G11C11/407 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4094 ,  G11C8/00

    CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C2207/005

    摘要： An XOR gate receives an input from a pair of read data lines to output a self-precharge signal when there is an increased potential difference between the paired read data lines. Thus, immediately after the increased potential difference between the paired read data lines occurs upon issuance of a read command, a precharge operation is autonomically performed. Therefore, no external precharge command is necessary when the read command is issued and thus a higher-speed operation is easily achieved.

    摘要翻译： 当成对的读取数据线之间存在增加的电位差​​时，XOR门从一对读取数据线接收输入以输出自我预充电信号。 因此，在发出读取命令之后立即发生配对读取数据线之间的增加的电位差​​之后，自动执行预充电操作。 因此，当发出读取命令时，不需要外部预充电命令，因此容易实现更高速度的操作。