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公开(公告)号：US20050010763A1
公开(公告)日：2005-01-13
申请号：US10858298
申请日：2004-06-02
申请人： Takayuki Matsui , Ryogo Yanagisawa
发明人： Takayuki Matsui , Ryogo Yanagisawa
CPC分类号： H04L63/0464 , H04N21/43632 , H04N21/43637 , H04N21/4367
摘要： A data transceiver includes: at least first and second encrypting/decrypting means each for encrypting and decrypting data; and transceiver means for transmitting and receiving data. In a first transmission mode, first transmission data encrypted by the first or second encrypting/decrypting means is transmitted by the transceiver means. In a first reception mode, first received data received by the transceiver means is decrypted by the first or second encrypting/decrypting means. In a second transmission mode, second transmission data decrypted by the first encrypting/decrypting means is encrypted by the second encrypting/decrypting means and then is transmitted by the transceiver means. In a second reception mode, second received data received by the transceiver means is decrypted by the second encrypting/decrypting means and then is encrypted by the first encrypting/decrypting means.
摘要翻译： 数据收发器包括：用于加密和解密数据的至少第一和第二加密/解密装置; 以及用于发送和接收数据的收发器装置。 在第一传输模式中，由第一或第二加密/解密装置加密的第一传输数据由收发机装置发送。 在第一接收模式中，由收发器装置接收的第一接收数据由第一或第二加密/解密装置解密。 在第二传输模式中，由第一加密/解密装置解密的第二传输数据由第二加密/解密装置加密，然后由收发机装置发送。 在第二接收模式中，由收发器装置接收的第二接收数据由第二加密/解密装置解密，然后被第一加密/解密装置加密。
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公开(公告)号：US20090028280A1
公开(公告)日：2009-01-29
申请号：US12280726
申请日：2007-01-09
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , G09G5/008 , G09G2370/12 , H04N21/242 , H04N21/4302
摘要： A clock control circuit 22 in a control circuit 21 provided in a transmitter 25 controls a gate circuit 12 based on an instruction from a microcomputer 32 to stop the output of the clock to a cable 115 for a first predetermined period of time. Then, a read-out circuit in the microcomputer 32 accesses an EDID 31 stored in an information storing circuit of a receiver 43 via the cable 115, and specifies the first predetermined period of time based on the EDID 31. A reconfiguration circuit 42 provided in the receiver 43 counts the clock-holding state, and resets at least one of the receiver 43 and a TV 114 if the clock has been stopped for a second predetermined period of time. This reset operation suppresses the display of noise on the TV 114. Therefore, the occurrence of noise due to mis-latching between the clock and the data can be reduced even after a signal switching that entails a change in the clock frequency.
摘要翻译： 设置在发送器25中的控制电路21中的时钟控制电路22基于来自微型计算机32的指令来控制门电路12，以在第一预定时间段内将时钟的输出停止到电缆115。 然后，微计算机32中的读出电路通过电缆115访问存储在接收机43的信息存储电路中的EDID 31，并基于EDID 31指定第一预定时间段。一种重配置电路42， 接收器43计数时钟保持状态，并且如果时钟已经停止了第二预定时间段，则复位接收器43和TV 114中的至少一个。 该复位操作抑制TV 114上的噪声的显示。因此，即使在需要时钟频率变化的信号切换之后，也可以减少由于时钟和数据之间的误锁而引起的噪声的发生。
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公开(公告)号：US20100245663A1
公开(公告)日：2010-09-30
申请号：US12376405
申请日：2007-07-31
CPC分类号： H03K5/135 , H03L7/18 , H03M9/00 , H04L7/0008
摘要： A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
摘要翻译： 一种用于接收并行数据信号和第一时钟信号并输出串行数据信号和第二时钟信号的半导体集成电路（10D），其中第一时钟产生电路（15）产生通过将第一时钟 信号X / Y。 第二时钟发生电路（11）具有可变的传输特性，并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分（12）将已被转换的并行数据信号 缩放器（16），与第四时钟信号同步地连接到串行数据信号。 分频器（13）产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器（14）有选择地输出第三和第五时钟信号之一作为第二时钟信号。
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公开(公告)号：US20090257453A1
公开(公告)日：2009-10-15
申请号：US12420506
申请日：2009-04-08
申请人： Ryogo Yanagisawa , Syuji Kato , Satoshi Takahashi
发明人： Ryogo Yanagisawa , Syuji Kato , Satoshi Takahashi
IPC分类号： H04J1/00
CPC分类号： H04N7/083 , G09G5/008 , G09G2370/12 , H03L7/093 , H03L7/18 , H04L7/0008
摘要： In an audio and video transmission apparatus, a frequency division parameter control unit outputs a frequency division parameter Pt, Qt for relating a pixel clock (frequency: pclk) for video data with an audio clock (frequency: ft) for audio data. An audio/video/packet multiplexing unit converts audio data and the frequency division parameter Pt, Qt into packets, and superimposes the packets into blanking intervals of video data, thereby producing transmission data. The frequency division parameter Pt, Qt satisfies a relationship represented by: pclk/Pt=ft/Qt=fpt, and cause fpt to have a value that falls outside of a predetermined band that is determined as the band of audio data.
摘要翻译： 在音频和视频传输装置中，分频参数控制单元输出用于将视频数据的像素时钟（频率：pclk）与用于音频数据的音频时钟（频率：ft）相关联的分频参数Pt，Qt。 音频/视频/分组复用单元将音频数据和分频参数Pt，Qt转换为分组，并将分组叠加到视频数据的消隐间隔中，从而产生传输数据。 分频参数Pt，Qt满足由pclk / Pt = ft / Qt = fpt表示的关系，并且使得fpt具有落在被确定为音频数据的频带的预定频带之外的值。
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5.发明授权公开(公告)号：US07512962B2
公开(公告)日：2009-03-31
申请号：US11129088
申请日：2005-05-13
申请人： Shoichi Gotoh , Yoshiki Kuno , Hiroyuki Iitsuka , Masazumi Yamada , Ryogo Yanagisawa , Hirotoshi Uehara , Toshiaki Tsuji
发明人： Shoichi Gotoh , Yoshiki Kuno , Hiroyuki Iitsuka , Masazumi Yamada , Ryogo Yanagisawa , Hirotoshi Uehara , Toshiaki Tsuji
CPC分类号： H04N21/4305 , H04L12/40117 , H04N5/04 , H04N5/4401 , H04N5/45 , H04N21/4316 , H04N21/434 , H04N21/4344 , H04N21/43632
摘要： A multichannel display data generating apparatus for generating data for displaying AV data on a multiscreen has a plurality of screens for displaying AV data of a plurality of channels, said apparatus comprising: input means for inputting AV data of a plurality of channels being transferred using a transport packet of a transport stream; a smaller number of PCR extracting means for extracting in a time-sharing mode the PCR of a plurality of channels displayed on said plurality of screens than the number of said plurality of screens; the same number of PLL means for establishing PLL synchronization by using said extracted PCR as the number of said plurality of screens; the same number of STC (system time clock) counter means for counting the times of the channels displayed on said plurality of screens by using the oscillation frequency of said PLL means as the number of said plurality of screens; AV decoding means for AV-decoding the AV data of the channels displayed on said multiscreen in AV synchronization with said STC counter means; and output means for outputting said AV-decoded AV data; and wherein said output AV data is displayed on said multiscreen.
摘要翻译： 一种用于生成用于在多画面上显示AV数据的数据的多声道显示数据产生装置具有用于显示多个声道的AV数据的多个画面，所述装置包括：输入装置，用于输入正在传送的多个频道的AV数据， 传输流的传输分组; 较少数量的PCR提取装置，用于以分时模式提取在所述多个屏幕上显示的多个频道的PCR，而不是所述多个屏幕的数量; 通过使用所述提取的PCR作为所述多个屏幕的数量来建立PLL同步的相同数量的PLL装置; 相同数量的STC（系统时钟）计数器装置，用于通过使用所述PLL装置的振荡频率作为所述多个屏幕的数量来对显示在所述多个屏幕上的频道的时间进行计数; AV解码装置，用于与所述STC计数器装置AV同步地AV解码在所述多画面上显示的频道的AV数据; 以及输出装置，用于输出所述AV解码的AV数据; 并且其中所述输出AV数据显示在所述多画面上。
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公开(公告)号：US20090052599A1
公开(公告)日：2009-02-26
申请号：US12279765
申请日：2006-11-30
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , G09G5/008 , G09G2320/0238 , H03L7/16 , H03M9/00 , H04N21/4122 , H04N21/43632
摘要： The present invention provides a transmitter capable of reducing the occurrence of noise when switching from the SD signal to the HD signal, for example. A microcomputer (151) controls a 10-times multiplication PLL (13) to increase the amount of jitter of a multiplied clock (CLK1×10) upon signal switching, i.e., when switching the frequency of an input clock (CLK1) from one to another. Alternatively, it controls a phase adjustment section (31) to increase the amount of jitter of a transmit clock (CLK2). Alternatively, it controls a fixed data producing section (61) to set transmit data (DATA2) to predetermined fixed data stored in a fixed data storing section (62).
摘要翻译： 本发明提供了一种例如在从SD信号切换到HD信号时能够减少噪声的发生的发送机。 微控制器（151）控制10倍乘法PLL（13），以便在信号切换时，即当将输入时钟（CLK1）的频率从一个切换到另一个时，增加倍增时钟（CLK1×10）的抖动量。 或者，它控制相位调整部分（31）以增加发送时钟（CLK2）的抖动量。 或者，它控制固定数据产生部分（61）将发送数据（DATA2）设置为存储在固定数据存储部分（62）中的预定固定数据。
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7.发明授权Clock signal switching device, clock signal switching method, data bus switching device, and data bus switching method 有权时钟信号切换装置，时钟信号切换方式，数据总线切换装置和数据总线切换方式公开(公告)号：US08026744B2
公开(公告)日：2011-09-27
申请号：US12861411
申请日：2010-08-23
IPC分类号： H03K17/00
摘要： A clock signal switching device includes: a plurality of signal synchronization generation means for generating mask signals and synchronized switching signals; a plurality of clock signal mask means for generating masked clock signals; a synchronized switching signal selection means for selecting one from among the synchronized switching signals; and a masked clock signal selection means for selecting one from among the masked clock signals.
摘要翻译： 时钟信号切换装置包括：多个信号同步产生装置，用于产生屏蔽信号和同步切换信号; 用于产生屏蔽时钟信号的多个时钟信号屏蔽装置; 同步切换信号选择装置，用于从同步切换信号中选择一个; 以及屏蔽时钟信号选择装置，用于从屏蔽的时钟信号中选择一个。
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公开(公告)号：US07472336B2
公开(公告)日：2008-12-30
申请号：US11035798
申请日：2005-01-18
申请人： Ryogo Yanagisawa
发明人： Ryogo Yanagisawa
CPC分类号： H04L1/0061 , H04L1/0045
摘要： A data detector detects an identification signal of a prescribed format from N-bit wide parallel input data (where N is a natural number). The data detector includes P first comparing sections (where P is a natural number), Q second comparing sections (where Q is a natural number), and a determining section. Each of the P first comparing sections compares one of first P data of continuous (P+Q) data in the parallel input data with a first pattern. Each of the Q second comparing sections compares one of Q data following the P data with a second pattern. The determining section determines whether the identification signal has been detected or not according to a comparison result of the P first comparing sections and a comparison result of the Q second comparing sections.
摘要翻译： 数据检测器从N位宽并行输入数据（其中N是自然数）检测规定格式的识别信号。 数据检测器包括P个第一比较部分（其中P是自然数），Q个第二比较部分（其中Q是自然数）和确定部分。 每个P个第一比较部分将并行输入数据中的连续（P + Q）数据的第一P数据与第一模式进行比较。 Q个第二比较部分中的每一个将P数据之后的Q数据与第二模式进行比较。 确定部分根据P个第一比较部分的比较结果和Q个第二比较部分的比较结果确定是否已经检测到识别信号。
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公开(公告)号：US20080056492A1
公开(公告)日：2008-03-06
申请号：US11907773
申请日：2007-10-17
IPC分类号： H04L9/00
CPC分类号： G11B20/00086 , G06F21/10 , G06F21/6209 , G06F2221/2107 , G11B20/0021
摘要： A key generation section 10 generates a key K to be used for cryptographic processing, based on an encrypted key data group EK. A key information retention/selection section 20 retains Lhe generated key and an intermediate key which was obtained when generating the key, and outputs the retained key information in accordance with selection information SEL. The key information is retained, e.g., in a storage circuit within the integrated circuitry, in a form which is not recognizable as a key. A content encryption/decryption section 30 restrains the cryptographic processing result DO from being outputted during key generation. When a heading pattern is detected during the cryptographic processing of an input signal DI, a reset/input enable signal generation circuit 60 switches an input enable signal IE to a disabled state, and outputs a reset signal RST after Lhe cryptographic processing has been completed.
摘要翻译： 密钥生成部10基于加密密钥数据组EK生成用于密码处理的密钥K. 密钥信息保留/选择部分20保留产生密钥的Lhe生成密钥和中间密钥，并根据选择信息SEL输出保留的密钥信息。 关键信息例如在集成电路内的存储电路中以不能被识别为密钥的形式被保留。 内容加密/解密部分30限制在密钥生成期间输出密码处理结果DO。 当在输入信号DI的加密处理期间检测到标题图案时，复位/输入使能信号产生电路60将输入使能信号IE切换到禁用状态，并且在加密处理完成之后输出复位信号RST。
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公开(公告)号：US07123306B1
公开(公告)日：2006-10-17
申请号：US09655394
申请日：2000-09-05
CPC分类号： H04N21/4344 , H04J3/0632 , H04N21/23608 , H04N21/4305 , H04N21/43632
摘要： A data transmitter for detecting a reference time stamp for use in reproducing a system clock from a transport packet data of a first transport stream, adding the detected reference time stamp as a header information to the transport packet data, converting the transport packet data and the header information into a second transport stream, and transmitting the second transport stream.
摘要翻译： 一种数据发送器，用于检测用于从第一传输流的传输分组数据再现系统时钟的参考时间戳，将检测到的参考时间戳作为标题信息添加到传输分组数据，转换传输分组数据和 头信息转换成第二传输流，并发送第二传输流。
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