摘要:
A multichannel display data generating apparatus for generating data for displaying AV data on a multiscreen has a plurality of screens for displaying AV data of a plurality of channels, said apparatus comprising: input means for inputting AV data of a plurality of channels being transferred using a transport packet of a transport stream; a smaller number of PCR extracting means for extracting in a time-sharing mode the PCR of a plurality of channels displayed on said plurality of screens than the number of said plurality of screens; the same number of PLL means for establishing PLL synchronization by using said extracted PCR as the number of said plurality of screens; the same number of STC (system time clock) counter means for counting the times of the channels displayed on said plurality of screens by using the oscillation frequency of said PLL means as the number of said plurality of screens; AV decoding means for AV-decoding the AV data of the channels displayed on said multiscreen in AV synchronization with said STC counter means; and output means for outputting said AV-decoded AV data; and wherein said output AV data is displayed on said multiscreen.
摘要:
A multichannel display data generating apparatus for generating data for displaying AV data on a multiscreen has a plurality of screens for displaying AV data of a plurality of channels, said apparatus comprising: input means for inputting AV data of a plurality of channels being transferred using a transport packet of a transport stream; a smaller number of PCR extracting means for extracting in a time-sharing mode the PCR of a plurality of channels displayed on said plurality of screens than the number of said plurality of screens; the same number of PLL means for establishing PLL synchronization by using said extracted PCR as the number of said plurality of screens; the same number of STC (system time clock) counter means for counting the times of the channels displayed on said plurality of screens by using the oscillation frequency of said PLL means as the number of said plurality of screens; AV decoding means for AV-decoding the AV data of the channels displayed on said multiscreen in AV synchronization with said STC counter means; and output means for outputting said AV-decoded AV data; and wherein said output AV data is displayed on said multiscreen.
摘要:
A multichannel display data generating apparatus displays AV data on a plurality of screens. A channel displayed on one of the screens is displayed without a program clock reference.
摘要:
The multichannel video processing unit of the invention includes: a decoding section for sequentially selecting a bit stream from a plurality of bit streams each including encoded data of an image of one channel, decoding the selected bit stream by one frame each, and outputting decoded data; a vertical filtering section for sequentially selecting a channel from a plurality of channels corresponding to the decoded images, performing vertical processing for the decoded data corresponding to the selected channel, and outputting vertically-processed data; a horizontal filtering section for sequentially selecting a channel according to the position at which the image is to be displayed, performing horizontal processing for the vertically-processed data corresponding to the selected channel, and outputting horizontally-processed data; and an output processing section for generating a video signal for display of images of a plurality of channels by synthesizing the horizontally-processed data and outputting the generated signal.
摘要:
A novel video signal correction system is disclosed, in which an average picture level detection circuit detects the average picture level (APL) of a luminance signal, and a coefficient calculation circuit calculates the amount of correction by the APL circuit. An adder adds an APL-corrected signal to a corrected luminance signal. A limiter circuit, on the other hand, limits the lower limit level of an input luminance signal. A divider circuit divides an output signal of the adder by an output signal of the limiter circuit, and the result is used to correct an input color signal. The color signal is thus capable of being corrected in accordance with the APL while at the same time preventing excessive correction of the color signal with a low brightness input.
摘要:
A multi-standard television receiver in accordance with the present invention includes a plurality of video signal processing blocks having tristate functions at their output terminals, at least one memory block used in common for a plurality of video signal processing blocks and a video signal processing selection means for selecting one of the video signal processing blocks and independently controlling the output terminals of the video signal processing blocks using elements having a tristate function and can reduce power consumption by working only a selected video signal processing block and stopping the other video signal processing blocks. Further, using elements having a tristate function, possibility of element breakdown at selection and control of the elements can be removed.
摘要:
A gradation corrector for use in a television receiver which can subject a signal at any luminance level to non-linear correction to provide optimum image quality. Memory stores therein luminance histogram of an input signal. On the basis of the data, a circuit detects a total frequency, a circuit detects luminance distribution, and a circuit detects the expanse of the luminance distribution. A circuit calculates a fixed value to be added. Further, a circuit detects a minimum luminance level, and a circuit detects an average luminance level. A circuit calculates an accumulation starting point and a circuit calculates an accumulation stopping point. An adder adds the calculated fixed value to the data in the memory. A circuit accumulates the results in the range from the accumulation starting point to the accumulation stopping point. The accumulation result is stored in memory. A circuit detects the maximum cumulative value, and a circuit normalizes all the data stored in the memory by use of this maximum value. The normalized data are stored in a memory. Thus, the input signal is subjected to optimum normalization by use of the normalized data.
摘要:
A semiconductor integrated circuit having a test circuit built therein is disclosed which consists of an A/D converter to be connected to a peripheral circuit, a digital circuit connected to the A/D converter, a digital signal switching device for selectively connecting to the output of the A/D converter and that of the digital circuit, and a boundary scan output circuit connected to the output of the digital signal switching device, wherein the digital signal switching device connects the A/D converter to the boundary scan output circuit in a normal mode, while the signal fetched in the boundary scan output circuit is outputted therefrom in test mode. Semiconductor integrated circuits having an analog circuit built therein and an analog integrated circuit in which a test circuit is built-in are also disclosed.
摘要:
The adsorbent for separation and recovery of CO is prepared by contacting an alumina or silica-alumina carrier with a mixed solution or dispersion of a cupric salt and a reducing agent in a solvent and, then, removing the solvent. The preferred cupric salt is cupric chloride.
摘要:
An I-axis phase pulse is allowed to be detected at the sampling point of a chrominance signal with a digitally-implemented circuit. A chrominance signal (sampling frequency f.sub.1) is subsampled by a frequency f.sub.2 (f.sub.1 /N) and subsampling pulses generated in N subsampling pulse generators 10 for N phases, the adjacent ones of the pulses being shifted by one clock (1/f.sub.1) with respect to one another. The subsampled chrominance signal is input to an I-axis determining circuit 17. The I-axis determining circuit operates to detect a maximum value M.sub.1 of a color burst signal (sampling frequency f.sub.1) and the data M.sub.2 after one clock and compare both of the values with each other. Based on the compared result, a selecting signal S.sub.4 is detected for selecting an I-axis phase pulse at the sampling point of the chrominance signal. A selecting circuit 18 selects, as an I-axis phase pulse S.sub.5, a proper one of the N sampling pulse for N phases based on the selecting signal and applies the I-axis phase pulse S.sub.5 to an (N+1)th subsampling circuit 19. The subsampling circuit 19 can provide an I-axis detected output S.sub.3 at the sampling point of the chrominance signal.