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    Steel wire rod
    5.
    发明授权
    Steel wire rod 有权
    钢丝杆

    公开(公告)号：US08092916B2

    公开(公告)日：2012-01-10

    申请号：US12409679

    申请日：2009-03-24

    申请人： Mikako Takeda ,  Shohei Nakakubo ,  Takashi Onishi ,  Masumi Nishimura ,  Hidenori Sakai ,  Tomotada Maruo

    发明人： Mikako Takeda ,  Shohei Nakakubo ,  Takashi Onishi ,  Masumi Nishimura ,  Hidenori Sakai ,  Tomotada Maruo

    IPC分类号： B32B15/02 ,  B32B15/04

    CPC分类号： C22C38/04 ,  C21D1/74 ,  C21D8/065 ,  C21D9/00 ,  C21D9/52 ,  C21D9/525 ,  C22C38/00 ,  C22C38/02 ,  Y10T428/256 ,  Y10T428/257 ,  Y10T428/265

    摘要： An FeO layer including fine crystal grains having random orientation is formed as inner layer scale on the surface of the steel wire rod containing C: 0.05-1.2 mass % (hereinafter referred to as “%”), Si: 0.01-0.50%, Mn: 0.1-1.5%, P: 0.02% or below, S: 0.02% or below, N: 0.005% or below, an Fe2SiO4 layer with the thickness: 0.01-1.0 μm is formed in the boundary face between the FeO layer of the inner layer scale and steel, and the thickness of the inner layer scale is 1-40% of the total scale thickness. In another aspect, the maximum grain size of the crystal grain of the inner layer scale is 5.0 μm or below and the average grain size is 2.0 μm or below.

    摘要翻译： 在含有C：0.05〜1.2质量％（以下称为“％”），Si：0.01-0.50％，Mn：0.01-0.50％的钢丝网的表面上形成包含具有随机取向的细晶粒的FeO层作为内层标尺 ：0.1-1.5％，P：0.02％以下，S：0.02％以下，N：0.005％以下，在FeO层的FeO层之间的边界面上形成厚度为0.01〜1.0μm的Fe 2 SiO 4层 内层刻度和钢，内层刻度的厚度为总刻度厚度的1-40％。 另一方面，内层鳞片的晶粒的最大粒径为5.0μm以下，平均粒径为2.0μm以下。

    Fabrication method for semiconductor interconnections
    6.
    发明授权
    Fabrication method for semiconductor interconnections 有权
    半导体互连的制造方法

    公开(公告)号：US07538027B2

    公开(公告)日：2009-05-26

    申请号：US11532796

    申请日：2006-09-18

    申请人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76882 ,  H01L21/76843 ,  H01L21/76867 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： There is provided a fabrication method for interconnections, capable of embedding a Cu-alloy in recesses in an insulating film, and forming a barrier layer on an interface between the an insulating film and Cu-interconnections, without causing a rise in electric resistivity of the interconnections when fabricating semiconductor interconnections of the Cu-alloy embedded in the recesses provided in the insulating film on a semiconductor substrate. The fabrication method for the interconnections may comprise the steps of forming the respective recesses having a minimum width not more than 0.15 μm, and a ratio of a depth thereof to the minimum width (a depth/minimum width ratio) not less than 1, forming a Cu-alloy film containing Ti in a range of 0.5 to 3 at %, and N in a range of 0.4 to 2.0 at % over the respective recesses, and subsequently, annealing the Cu-alloy film to not lower than 200° C., and pressurizing the Cu-alloy film to not less than 50 MPa to thereby embed the Cu-alloy film into the respective recesses.

    摘要翻译： 提供了一种用于互连的制造方法，其能够将铜合金嵌入绝缘膜中的凹陷中，并且在绝缘膜和Cu互连之间的界面上形成阻挡层，而不会引起电阻率的上升 当制造嵌入在设置在半导体衬底上的绝缘膜中的凹部中的Cu合金的半导体互连时，互连。 互连的制造方法可以包括以下步骤：形成具有不大于0.15μm的最小宽度的相应凹槽，以及其深度与最小宽度（深度/最小宽度比）的比不小于1，形成 在各凹部中含有0.5〜3原子％的Ti，N为0.4〜2.0原子％的Ti的Cu合金膜，然后将Cu合金膜退火至200℃以上。 并将Cu合金膜加压至50MPa以上，从而将Cu合金膜嵌入各凹部。

    CU WIRE IN SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF
    7.
    发明申请
    CU WIRE IN SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREOF 审中-公开
    CU线上半导体器件及其制造方法

    公开(公告)号：US20100052171A1

    公开(公告)日：2010-03-04

    申请号：US12515538

    申请日：2007-11-19

    申请人： Hirotaka Ito ,  Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno

    发明人： Hirotaka Ito ,  Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno

    IPC分类号： H01L23/532 ,  H01L21/768

    CPC分类号： C22C9/00 ,  C23C14/024 ,  C23C14/165 ,  H01L21/2855 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A Cu wire in a semiconductor device according to the present invention is a Cu wire embedded into wiring gutters or interlayer connective channels formed in an insulating film on a semiconductor substrate and the Cu wire comprises: a barrier layer comprising TaN formed on the wiring gutter side or the interlayer connective channel side; and a wire main body comprising Cu comprising one or more elements selected from the group consisting of Pt, In, Ti, Nb, B, Fe, V, Zr, Hf, Ga, Tl, Ru, Re, and Os in a total content of 0.05 to 3.0 atomic percent. The Cu wire in a semiconductor device according to the present invention is excellent in adhesiveness between the wire main body and the barrier layer.

    摘要翻译： 根据本发明的半导体器件中的Cu线是嵌入到形成在半导体衬底上的绝缘膜中的布线沟或层间连接沟道中的Cu线，并且所述Cu线包括：形成在布线槽侧的TaN的阻挡层 或层间连接通道侧; 以及包含Cu，其包含选自Pt，In，Ti，Nb，B，Fe，V，Zr，Hf，Ga，Tl，Ru，Re和Os中的一种以上的元素，总含量 为0.05〜3.0原子％。 根据本发明的半导体器件中的Cu线在线主体和阻挡层之间的粘附性优异。

    Metal thin film for interconnection of semiconductor device
    8.
    发明授权
    Metal thin film for interconnection of semiconductor device 有权
    用于半导体器件互连的金属薄膜

    公开(公告)号：US07928573B2

    公开(公告)日：2011-04-19

    申请号：US11465626

    申请日：2006-08-18

    申请人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda

    发明人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda

    IPC分类号： H01L23/48

    CPC分类号： H01L23/53233 ,  H01L21/2855 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal thin film used in fabricating a damascene interconnection of a semiconductor device which exhibits excellent high temperature fluidity during high pressure annealing, and which can fabricate an interconnection for a semiconductor device which has a low electric resistance and stable high quality is provided. Also provided is an interconnection for a semiconductor device. More specifically, a metal thin film for use as an interconnection of a semiconductor device comprising a Cu alloy containing N at a content of not less than 0.4 at % to not more than 2.0 at %; and an interconnection for a semiconductor device fabricated by forming the metal thin film on an insulator film which is formed on a semiconductor substrate and which has grooves formed therein, and filling the metal thin film in the interior of the grooves by a high pressure annealing process are provided.

    摘要翻译： 提供了用于制造半导体器件的镶嵌互连的金属薄膜，其在高压退火期间表现出优异的高温流动性，并且可以制造具有低电阻和稳定高质量的半导体器件的互连。 还提供了用于半导体器件的互连。 更具体地说，一种用作半导体器件的互连的金属薄膜，其包含含有不小于0.4原子％至不大于2.0原子％的含有N的Cu合金; 以及通过在形成在半导体衬底上并形成有凹槽的绝缘体膜上形成金属薄膜而制造的半导体器件的互连，并且通过高压退火工艺在槽内填充金属薄膜 被提供。

    Method of fabricating semiconductor interconnections
    9.
    发明授权
    Method of fabricating semiconductor interconnections 失效
    制造半导体互连的方法

    公开(公告)号：US07781339B2

    公开(公告)日：2010-08-24

    申请号：US11765006

    申请日：2007-06-19

    申请人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    发明人： Takashi Onishi ,  Mikako Takeda ,  Masao Mizuno ,  Susumu Tsukimoto ,  Tatsuya Kabe ,  Toshifumi Morita ,  Miki Moriyama ,  Kazuhiro Ito ,  Masanori Murakami

    IPC分类号： H01L21/44 ,  H01L21/4763

    CPC分类号： H01L21/76843 ,  H01L21/76864 ,  H01L21/76867

    摘要： A method of fabricating semiconductor interconnections is provided which can form a Ti-rich layer as a barrier layer and which can embed pure Cu material as interconnection material into every corner of grooves provided in an insulating film even when the grooves have a narrow minimum width and are deep. The method may include the steps of forming one or more grooves in an insulating film on a semiconductor substrate, the recess having a minimum width of 0.15 μm or less and a ratio of a depth of the groove to the minimum width thereof (depth/minimum width) of 1 or more, forming a Cu alloy thin film containing 0.5 to 10 atomic % of Ti in the groove of the insulated film along a shape of the groove in a thickness of 10 to 50 nm, forming a pure Cu thin film in the groove with the Cu alloy thin film attached thereto, and annealing the substrate with the films at 350° C. or more to allow the Ti to be precipitated between the insulating film and the Cu alloy thin film.

    摘要翻译： 提供一种制造半导体互连的方法，其可以形成富Ti层作为阻挡层，并且即使当沟槽具有窄的最小宽度时，也可以将纯Cu材料作为互连材料嵌入设置在绝缘膜中的沟槽的每个角落，并且 很深 该方法可以包括以下步骤：在半导体衬底上的绝缘膜中形成一个或多个凹槽，凹槽具有0.15μm或更小的最小宽度以及凹槽的深度与其最小宽度的比（深度/最小值 宽度）为1以上，沿着形状为10〜50nm的槽的形状，在绝缘膜的槽内形成含有0.5〜10原子％的Ti的Cu合金薄膜，形成纯Cu薄膜 与Cu合金薄膜连接的槽，并使膜在350℃以上退火，使Ti在绝缘膜与Cu合金薄膜之间析出。

    METAL THIN FILM FOR INTERCONNECTION OF SEMICONDUCTOR DEVICE, INTERCONNECTION FOR SEMICONDUCTOR DEVICE, AND THEIR FABRICATION METHOD
    10.
    发明申请
    METAL THIN FILM FOR INTERCONNECTION OF SEMICONDUCTOR DEVICE, INTERCONNECTION FOR SEMICONDUCTOR DEVICE, AND THEIR FABRICATION METHOD 有权
    用于半导体器件互连的金属薄膜，用于半导体器件的互连及其制造方法

    公开(公告)号：US20070145586A1

    公开(公告)日：2007-06-28

    申请号：US11465626

    申请日：2006-08-18

    申请人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda

    发明人： Takashi Onishi ,  Masao Mizuno ,  Mikako Takeda

    IPC分类号： H01L23/48

    CPC分类号： H01L23/53233 ,  H01L21/2855 ,  H01L21/76882 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A metal thin film used in fabricating a damascene interconnection of a semiconductor device which exhibits excellent high temperature fluidity during high pressure annealing, and which can fabricate an interconnection for a semiconductor device which has a low electric resistance and stable high quality is provided. Also provided is an interconnection for a semiconductor device.More specifically, a metal thin film for use as an interconnection of a semiconductor device comprising a Cu alloy containing N at a content of not less than 0.4 at % to not more than 2.0 at %; and an interconnection for a semiconductor device fabricated by forming the metal thin film on an insulator film which is formed on a semiconductor substrate and which has grooves formed therein, and filling the metal thin film in the interior of the grooves by a high pressure annealing process are provided.

    摘要翻译： 提供了用于制造半导体器件的镶嵌互连的金属薄膜，其在高压退火期间表现出优异的高温流动性，并且可以制造具有低电阻和稳定高质量的半导体器件的互连。 还提供了用于半导体器件的互连。 更具体地说，一种用作半导体器件的互连的金属薄膜，其包含含有不小于0.4原子％至不大于2.0原子％的含有N的Cu合金; 以及通过在形成在半导体衬底上并形成有凹槽的绝缘体膜上形成金属薄膜而制造的半导体器件的互连，并且通过高压退火工艺在槽内填充金属薄膜 被提供。