公开(公告)号：US5723986A

公开(公告)日：1998-03-03

申请号：US659000

申请日：1996-06-04

申请人： Takeshi Nakashiro ,  Isao Abe ,  Takeshi Suyama ,  Junichi Machida

发明人： Takeshi Nakashiro ,  Isao Abe ,  Takeshi Suyama ,  Junichi Machida

IPC分类号： H03K19/0185 ,  H03K3/356 ,  H03K19/0948

CPC分类号： H03K3/356113

摘要： A level shifting circuit has a high-level shifter connected to a first high voltage and to a first low voltage, for amplifying the peak voltage of an input signal; a low-level shifter connected to a second high voltage lower than the first high voltage and to a second low voltage lower than the first low voltage, for amplifying the trough voltage of the input signal; a high-voltage controlling transistor connected to the first high voltage and to an output node and turned on and off according to the output of the high-level shifter; and a low-voltage controlling transistor connected to the output node and to the second low voltage and turned on and off according to the output of the low-level shifter complementarily to the high-voltage controlling transistor. The level shifting circuit is capable of amplifying both the peak and trough voltages of an input signal.

摘要翻译： 电平移位电路具有连接到第一高电压和第一低电压的高电平移位器，用于放大输入信号的峰值电压; 连接到低于第一高电压的第二高电压和低于第一低电压的第二低电压的低电平移位器，用于放大输入信号的谷电压; 连接到第一高电压的高电压控制晶体管和输出节点，并根据高电平移位器的输出导通和截止; 以及低压控制晶体管，其连接到所述输出节点并连接到所述第二低电压，并根据所述低电平移位器的输出与所述高电压控制晶体管互补地导通和截止。 电平移位电路能够放大输入信号的峰值电压和谷底电压。

公开(公告)号：US5835076A

公开(公告)日：1998-11-10

申请号：US544479

申请日：1995-10-18

申请人： Junichi Machida ,  Nobuyuki Kawano ,  Takeshi Suyama

发明人： Junichi Machida ,  Nobuyuki Kawano ,  Takeshi Suyama

IPC分类号： G02F1/133 ,  G06F3/033 ,  G06F3/041 ,  G09G3/18 ,  G09G3/36

CPC分类号： G06F3/0412 ,  G09G3/3692

摘要： A pen input liquid crystal display has row electrodes, column electrodes orthogonal to the row electrodes, and a liquid crystal layer interposed between the row and column electrodes. A pen input detecting signal is applied to one of the column electrodes, and display signals to the other column electrodes. The column electrode that receives the pen input detecting signal is sequentially shifted among the column electrodes, to simultaneously carry out a pen input scanning operation and an image displaying operation.

摘要翻译： 笔输入液晶显示器具有行电极，与行电极正交的列电极和插在行电极与列电极之间的液晶层。 笔输入检测信号被施加到列电极中的一个，并向其它列电极显示信号。 接收笔输入检测信号的列电极在列电极之间顺序移位，以同时执行笔输入扫描操作和图像显示操作。

公开(公告)号：US5124763A

公开(公告)日：1992-06-23

申请号：US651435

申请日：1991-02-07

申请人： Tsutomu Takahasi ,  Takeshi Suyama ,  Satoshi Suzuki ,  Isao Abe ,  Akihiro Sueda

发明人： Tsutomu Takahasi ,  Takeshi Suyama ,  Satoshi Suzuki ,  Isao Abe ,  Akihiro Sueda

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/402 ,  H01L27/0927 ,  H01L29/7813 ,  H01L29/7835

摘要： A P-well region is provided in a semiconductor substrate of N-type. A P-channel MOSFET is arranged in the N-type substrate while an N-channel MOSFET is arranged in the P-well region. The drain regions of the respective MOSFETs consist of high concentration impurity diffused regions and low concentration impurity diffused regions arranged about the respective high concentration impurity diffused regions. Also, a drain electrode is provided to cover the entire of the high and low concentration impurity diffused regions.

公开(公告)号：US06933915B2

公开(公告)日：2005-08-23

申请号：US09892697

申请日：2001-06-28

申请人： Kiyoshi Hidaka ,  Takeshi Suyama

发明人： Kiyoshi Hidaka ,  Takeshi Suyama

IPC分类号： G02F1/133 ,  G09G1/16 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G09G5/39

CPC分类号： G09G5/001 ,  G09G3/3611 ,  G09G3/3688 ,  G09G5/39 ,  G09G2310/027 ,  G09G2320/0247 ,  G09G2360/18

摘要： A small chip size and high picture quality, and also a quick CPU access operation to memory are achieved for a semiconductor device for driving liquid crystals. The semiconductor device includes a single-port memory that stores display-data to be displayed on a liquid crystal displaying section, a liquid crystal driver that retrieves the display-data stored in the single-port memory on a specific cycle and sends the display-data to the liquid crystal displaying section and a controller that controls the liquid crystal driver so that, when a CPU does not have access to the single-port memory, the display-data is retrieved from the single-port memory to the liquid crystal driver on the specific cycle and the retrieved data is sent to the liquid crystal displaying section, whereas, when the CPU has access to the single-port memory while the data is being retrieved from the single-port memory to the liquid crystal driver, a priority is given to the CPU so that the CPU starts an access operation while the liquid crystal driver stops a display-data retrieval operation, and on completion of the access operation, the liquid crystal driver starts again the display-data retrieval operation.

摘要翻译： 对于用于驱动液晶的半导体器件，实现了小芯片尺寸和高图像质量以及对存储器的快速CPU访问操作。 半导体器件包括存储要显示在液晶显示部分上的显示数据的单端口存储器，以特定周期检索存储在单端口存储器中的显示数据的液晶驱动器， 液晶显示部分的数据和控制液晶驱动器的控制器，使得当CPU不能访问单端口存储器时，将显示数据从单端口存储器检索到液晶驱动器 在特定循环中，检索到的数据被发送到液晶显示部分，而当CPU从单端口存储器检索数据到液晶驱动器时CPU访问单端口存储器时，优先权 被提供给CPU，使得CPU在液晶驱动器停止显示数据检索操作时开始访问操作，并且在完成访问操作时，液晶驱动器再次启动 显示数据检索操作。

公开(公告)号：US6028598A

公开(公告)日：2000-02-22

申请号：US856152

申请日：1997-05-14

申请人： Takeshi Suyama ,  Shoichi Iwamoto

发明人： Takeshi Suyama ,  Shoichi Iwamoto

IPC分类号： G02F1/133 ,  G09G3/18 ,  G09G3/36

CPC分类号： G09G3/18 ,  G09G3/3681 ,  G09G3/3692 ,  G09G3/3696 ,  G09G2330/02

摘要： Five voltage dividing resistors are connected in series between the nodes of external power supply voltages to obtain first to fourth divided voltages. A first power amplifier of an Ntop type for impedance conversion is connected to a node of the first voltage. A second power amplifier of a Ptop type for impedance conversion is connected to a node of the second voltage. A third power amplifier of the Ntop type for impedance conversion is connected to a node of the third voltage. A fourth power amplifier of the Ptop type for impedance conversion is connected to a node of the fourth voltage. In each of the first and third power amplifiers of the Ntop type, the ability of causing a current to flow out of the amplifier from the output terminal is set to be high, and the ability of causing a current to flow into the amplifier from the output terminal is set to be low. In each of the second and fourth power amplifiers of the Ptop type, the ability of causing a current to flow into the amplifier from the output terminal is set to be high, and the ability of causing a current to flow out of the amplifier from the output terminal is set to be low.

摘要翻译： 五个分压电阻串联连接在外部电源电压的节点之间，以获得第一至第四分压。 用于阻抗转换的Ntop类型的第一功率放大器连接到第一电压的节点。 用于阻抗转换的Ptop类型的第二功率放大器连接到第二电压的节点。 用于阻抗转换的Ntop类型的第三功率放大器连接到第三电压的节点。 用于阻抗转换的Ptop类型的第四功率放大器连接到第四电压的节点。 在Ntop型的第一和第三功率放大器的每一个中，使得电流从输出端子流出放大器的能力被设置为高，并且使得电流从 输出端子设置为低电平。 在Ptop类型的第二和第四功率放大器的每一个中，使电流从输出端子流入放大器的能力被设置为高，并且使电流从放大器流出的能力 输出端子设置为低电平。

公开(公告)号：US5880630A

公开(公告)日：1999-03-09

申请号：US729294

申请日：1996-10-10

申请人： Shoichi Iwamoto ,  Takeshi Suyama

发明人： Shoichi Iwamoto ,  Takeshi Suyama

IPC分类号： H03F1/30 ,  H03F3/00 ,  H03F1/14

CPC分类号： H03F1/303 ,  H03F3/005

摘要： A gain stage and offset voltage elimination method. The gain stage includes an amplifier, condensers and a number of switches. The switches are arranged to discharge the condensers and then charge the condensors to the offset voltage during an initialize period. When an input voltage is applied to the gain stage, the condensers do not act as capacitive loads for the amplifier. The gain stage can thus more quickly charge the condensers since the charging speed is approximately equal to the slew rate of the amplifier. The period for initializing the gain stage can be shortened while minimizing the current consumed.

摘要翻译： 增益级和失调电压消除方法。 增益级包括放大器，电容器和多个开关。 开关被布置成放电冷凝器，然后在初始化期间将冷凝器充电到偏移电压。 当输入电压施加到增益级时，电容器不会作为放大器的容性负载。 因为增益级可以更快速地对电容器充电，因为充电速度近似等于放大器的转换速率。 可以缩短初始化增益级的周期，同时使消耗的电流最小化。