公开(公告)号：US20240097620A1

公开(公告)日：2024-03-21

申请号：US18452204

申请日：2023-08-18

Applicant: NXP B.V.

Inventor： Vincent Geffroy

IPC: H03F1/30 ,  H03F3/45

CPC classification number: H03F1/303 ,  H03F3/45179 ,  H03F2200/141

Abstract: An error amplifier including a differential pair circuit, a resistive device, a low voltage capacitor, and a protection device. The differential pair circuit is coupled between an upper supply node and a lower supply node with first and second intermediate nodes and is responsive to a difference between a reference voltage and a feedback voltage for driving a control voltage developed on the second intermediate node. The resistive device is coupled between the second intermediate node and a low voltage node, and the low voltage capacitor and the protection device are coupled between the low voltage node and the lower supply node. The protection device is dynamically controlled by the first intermediate node to prevent the low voltage node from exceeding a predetermined maximum level. The protection device may be a transistor having size parameters based on voltage characteristics of the first intermediate node during expected operating conditions.

公开(公告)号：US11929717B2

公开(公告)日：2024-03-12

申请号：US17582338

申请日：2022-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahadevan Shankara Venkiteswaran ,  Arun Singh ,  Jofin Vadakkeparasseril Joseph

IPC: H03F1/52 ,  H03F1/30 ,  H03F3/00 ,  H03F3/45

CPC classification number: H03F1/303 ,  H03F1/52 ,  H03F3/005 ,  H03F3/45632

Abstract: An output stage of an operational amplifier includes a low voltage (LV) metal oxide semiconductor (MOS) device and a dynamic current limit circuit. An output current of the operational amplifier flows through the LV MOS device. The dynamic current limit circuit is configured to sense a drain voltage of the LV MOS device and increase a clamping voltage for the LV MOS device when the drain voltage of the LV MOS device is less than a threshold voltage.

公开(公告)号：US11876490B2

公开(公告)日：2024-01-16

申请号：US17587105

申请日：2022-01-28

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Shylaja Krishnan ,  Akshay Yashwant Jadhav ,  Tallam Vishwanath

IPC: H03F1/30 ,  G05F3/26

CPC classification number: H03F1/303 ,  G05F3/267 ,  H03F2200/375 ,  H03F2200/447 ,  H03F2200/468

Abstract: Described embodiments include an integrated circuit for temperature gradient compensation of a bandgap voltage. A bandgap core circuit has a bandgap feedback input, a bandgap adjustment input and a bandgap reference output. A resistor is coupled between the bandgap adjustment input and a ground terminal. An offset and slope correction circuit has an offset correction output that is coupled to the bandgap adjustment input. A signal at the offset correction output is trimmed at an ambient temperature. A thermal error cancellation (TEC) circuit has a TEC output coupled to the bandgap adjustment input. The TEC circuit includes first and second temperature sensors that are located apart from each other. A signal at the TEC output is responsive to temperatures at the first and second temperature sensors. An amplifier has an amplifier input and an amplifier output. The amplifier input is coupled to the bandgap reference output.

公开(公告)号：US20230170315A1

公开(公告)日：2023-06-01

申请号：US18158574

申请日：2023-01-24

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Koji FURUTANI

IPC: H01L23/66 ,  H01L23/00 ,  H04B1/44 ,  H03F1/30 ,  H03F1/56 ,  H01L23/13 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/13 ,  H01L23/49827 ,  H01L24/32 ,  H01L25/16 ,  H03F1/303 ,  H03F1/565 ,  H04B1/44 ,  H01L2223/665 ,  H01L2223/6616 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/32225 ,  H01L2924/14215 ,  H03F2200/27 ,  H03F2200/294 ,  H03F2200/465 ,  H03F2200/468

Abstract: A radio-frequency module includes a multilayer substrate, a first semiconductor device, a second semiconductor device, and an anisotropic conductive resin component. The multilayer substrate includes a plurality of stacked layers, and has a first major face and a second major face. The first major face includes a first recess. The first semiconductor device is mounted over a bottom face of the first recess with the anisotropic conductive resin component interposed therebetween. The second semiconductor device is mounted over the first major face so as to overlie the first recess. The first semiconductor device is connected with a metallic via that extends through a portion of the multilayer substrate from the bottom face of the first recess to the second major face.

公开(公告)号：US09985586B2

公开(公告)日：2018-05-29

申请号：US15073897

申请日：2016-03-18

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Hee Kim

IPC: H03F1/30 ,  H03F1/22 ,  H03F3/19 ,  H04B1/38 ,  H03F3/193 ,  H03F3/72

CPC classification number: H03F1/303 ,  H03F1/22 ,  H03F3/193 ,  H03F3/72 ,  H03F2203/7206 ,  H03F2203/7233 ,  H03F2203/7236 ,  H03F2203/7239 ,  H04B1/38

Abstract: A front end circuit includes a bypass circuit comprising a first bypass switch and a second bypass switch configured to bypass a signal to a first terminal according to switching operations of the first bypass switch and the second bypass switch; and an amplifier connected in parallel to the bypass circuit and configured to amplify the signal.

公开(公告)号：US20180138866A1

公开(公告)日：2018-05-17

申请号：US15808458

申请日：2017-11-09

Applicant: SKYWORKS SOLUTIONS, INC.

Inventor： Bang Li Liang ,  Thomas Obkircher ,  Adrian John Bergsma ,  Peter Harris Robert Popplewell

IPC: H03F1/30 ,  H03K3/356 ,  H03F3/19 ,  H03K3/011

CPC classification number: H03F1/303 ,  H03F1/301 ,  H03F3/19 ,  H03K3/011 ,  H03K3/354 ,  H03K3/356086 ,  H03K3/356182

Abstract: Methods and systems are provided for generating an oscillating signal for use as a clock in digital logic timing. The oscillating signal is generated via a differential RC relaxation oscillator including an oscillator core and biasing circuitry. The oscillator core may be configured such that the oscillating signal it generates is substantially sinusoidal or pseudo-sinusoidal and contains less harmonic content relative to a square wave signal. The biasing circuitry may be configured to have a reduced dependence on temperature so that the biasing values it provides vary less with temperature.

公开(公告)号：US09847773B2

公开(公告)日：2017-12-19

申请号：US15491476

申请日：2017-04-19

Applicant: Cirrus Logic, Inc.

Inventor： John L. Melanson ,  Paul Lesso

IPC: H03K3/01 ,  H03K3/011

CPC classification number: H03K3/011 ,  H03F1/303 ,  H03F3/2171 ,  H03K7/08 ,  H03M1/822

Abstract: Noise introduced in an output signal of a pulse-width modulator (PWM) may be reduced by changing the time duration that a switch is driving the output node. Because the power supplies coupled to the switches are the source of noise in the output signal of the PWM, the time duration that the power supplies are driving the output may be reduced to obtain a subsequent reduction in noise in the output signal. For example, when a small signal is desired to be output by the PWM, the switches may be operated for shorter time durations. Thus, the switches couple the noise sources to ground for a duration of a cycle to reduce contribution of noise to the output. But, when a larger signal is desired to be output by the PWM, the switches may be operated for longer time durations or the conventional time durations described above.

公开(公告)号：US20170302236A1

公开(公告)日：2017-10-19

申请号：US15631035

申请日：2017-06-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Teruaki OSHITA

IPC: H03F3/217 ,  H03F3/00 ,  H03F1/56 ,  H03F3/04 ,  H03F1/30

CPC classification number: H03F3/2178 ,  H03F1/0277 ,  H03F1/0288 ,  H03F1/303 ,  H03F1/56 ,  H03F1/565 ,  H03F3/005 ,  H03F3/04 ,  H03F3/191 ,  H03F3/195 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/111 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2203/7209 ,  H03F2203/7233 ,  H03F2203/7236 ,  H03F2203/7239

Abstract: An amplification circuit includes a first switching circuit that includes input terminals and first and second output terminals and that puts the second output terminal into an open state with respect to the input terminals while selectively putting the first output terminal into a state of being connected to any of the input terminals or selectively puts the second output terminal into a state of being connected to any of input terminals while putting the first output terminal into a state of being open with respect to the input terminals; a matching network that is connected to the first output terminal; an amplifier that is connected to an output side of the matching network; a second switching circuit that is connected to an output side of the amplifier; and a bypass path that electrically connects the second output terminal and an output terminal of the second switching circuit. The amplifier is a variable-gain amplifier.

公开(公告)号：US09755595B1

公开(公告)日：2017-09-05

申请号：US15130691

申请日：2016-04-15

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Saihua Lin

IPC: H03G3/30 ,  H03G1/00 ,  H03K19/21 ,  H03F3/193 ,  H03F1/02 ,  H03F1/30

CPC classification number: H03G1/0029 ,  H03F1/0261 ,  H03F1/30 ,  H03F1/301 ,  H03F1/302 ,  H03F1/303 ,  H03F3/193 ,  H03F2200/294 ,  H03F2200/451 ,  H03F2200/492 ,  H03G1/0088 ,  H03G3/001 ,  H03K19/21

Abstract: A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.

公开(公告)号：US20170222629A1

公开(公告)日：2017-08-03

申请号：US15491476

申请日：2017-04-19

Applicant: Cirrus Logic, Inc.

Inventor： John L. Melanson ,  Paul Lesso

IPC: H03K3/011

CPC classification number: H03K3/011 ,  H03F1/303 ,  H03F3/2171 ,  H03K7/08 ,  H03M1/822

Abstract: Noise introduced in an output signal of a pulse-width modulator (PWM) may be reduced by changing the time duration that a switch is driving the output node. Because the power supplies coupled to the switches are the source of noise in the output signal of the PWM, the time duration that the power supplies are driving the output may be reduced to obtain a subsequent reduction in noise in the output signal. For example, when a small signal is desired to be output by the PWM, the switches may be operated for shorter time durations. Thus, the switches couple the noise sources to ground for a duration of a cycle to reduce contribution of noise to the output. But, when a larger signal is desired to be output by the PWM, the switches may be operated for longer time durations or the conventional time durations described above.