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1.发明授权Controlling synchronization in a system having a plurality of units when a unit is disconnected from or connected to the system that is active 失效当单元与活动的系统断开或连接到系统时，控制具有多个单元的系统中的同步
公开(公告)号：US5463663A
公开(公告)日：1995-10-31
申请号：US189056
申请日：1994-01-31
CPC分类号： H04L7/0083 , H04J3/0685
摘要： An apparatus for controlling synchronization in a system having at least first and second units each having internal circuits includes signal paths through which a control signal output from a second unit is sent to a first unit and a control signal output from the first unit is sent to the second unit. A first preparatory process part carries out a process to place the internal circuits of the second unit in an operating state when the second unit is connected to the system and for outputting a control signal to the signal paths. A first function mask control part is provided for stopping the operation of the internal circuits of the second unit when a control signal from the first unit is not received by the second unit, and for restarting the operation of the internal circuits when the control signal is received. A second preparatory process part carries out a process to place the internal circuits of the first unit in an operating state when the control signal from the second unit is received by the first unit, and for outputting a control signal to the signal paths. A second function mask control part is provided for stopping the operation of the internal circuits of the first unit when the control signal is not received, and for re-starting the operation of the internal circuits when the control signal is received.
摘要翻译： 一种用于控制具有至少具有内部电路的第一和第二单元的系统中的同步的装置，包括将从第二单元输出的控制信号发送到第一单元的信号路径，并将从第一单元输出的控制信号发送到 第二单位。 第一准备处理部分执行将第二单元的内部电路放置在操作状态的过程，当第二单元连接到系统并将控制信号输出到信号路径时。 提供第一功能掩模控制部件，用于当来自第一单元的控制信号未被第二单元接收时停止第二单元的内部电路的操作，并且当控制信号为 收到了 第二准备处理部分执行将来自第二单元的控制信号由第一单元接收并将控制信号输出到信号路径时将第一单元的内部电路置于操作状态的处理。 提供第二功能掩模控制部件，用于在不接收到控制信号时停止第一单元的内部电路的操作，并且在接收到控制信号时重新启动内部电路的操作。
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公开(公告)号：US5548716A
公开(公告)日：1996-08-20
申请号：US283780
申请日：1994-08-01
申请人： Takumi Maruyama , Noriyuki Yokoshi
发明人： Takumi Maruyama , Noriyuki Yokoshi
CPC分类号： G06F11/2071 , G06F11/3055 , G11C29/74
摘要： A main controller of a recording medium dualization system reads, when the power is turned on, three types of information: USE information (status information of a recording medium of each medium board) indicating whether or not the medium can be used; ACT information indicating which of the recording mediums is or was used in an active system; and PWON information indicating whether or not the power for the recording medium is turned on, whereupon the main controller sets the information to denote that the master system is an active system and executes a mirroring process whereby the USE information and the PWON information of the slave system are identical to the master system. When it is found that the recording medium of the master system is removed, on the basis of the USE and ACT information, the slave system is switched to an active system, and the corresponding information setting is performed. When it is found that the recording medium of the master system is mounted, on the basis of the PWON information, the USE information and the PWON information of the slave system are mirrored onto the master system.
摘要翻译： 记录介质二次化系统的主控制器在电源接通时读取三种类型的信息：指示是否可以使用介质的USE信息（每个介质板的记录介质的状态信息） 指示在活动系统中使用哪个记录介质的ACT信息; PWON信息表示记录介质的电源是否被接通，主控制器设定信息以表示主系统是活动系统，并执行镜像处理，由此使用信息和从属设备的PWON信息 系统与主系统相同。 当发现主系统的记录介质被删除时，基于USE和ACT信息，从系统被切换到活动系统，并执行相应的信息设置。 当发现主系统的记录介质被安装时，基于PWON信息，从系统的USE信息和PWON信息被镜像到主系统上。
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3.发明授权Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation 失效多个同时未解决的分支评估的观察点的处理器结构和方法
公开(公告)号：US5655115A
公开(公告)日：1997-08-05
申请号：US482075
申请日：1995-06-07
CPC分类号： G06F9/3004 , G06F11/1407 , G06F9/30043 , G06F9/3834 , G06F9/3836 , G06F9/384 , G06F9/3842 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3865
摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, and such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.
摘要翻译： 基于预定的超时条件或时间间隔形成超时检查点，因为上一次检查点形成而不是形成检查点，以便仅仅依赖于解码的指令属性来存储当前的处理器状态。 例如，这种超时条件可以包括发出的指令的数量或经过的时钟周期的数量。 超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。 只要指令窗口大小大于检查点边界内的指令的最大数量，处理器可以在发生异常的情况下比基于指令解码的检查点技术更快地恢复基于超时的检查点状态，并且这种方法消除了处理器状态 恢复依赖于指令窗口大小。 超时检查点可以用常规检查点或新颖的逻辑和物理寄存器重命名映射检查点技术来实现。 超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。
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公开(公告)号：US5442777A
公开(公告)日：1995-08-15
申请号：US201808
申请日：1994-02-25
CPC分类号： G06F11/3636 , G06F11/3466
摘要： A firmware trace data acquisition method is constituted such that there are provided a monitoring part for monitoring firmware processes and a DMA part for transferring data to a trace data storing part in accordance with an instruction from the monitoring part, such that labels are attached to the plurality of process modules stored in a firmware storing part, and such that each of the process modules activated notifies the monitoring part of the label attached to itself. The monitoring part latches the label that it is notified of and monitors the execution of the corresponding process such that, when an abnormality is detected during the execution, the monitoring part controls the DMA part so as to transfer detailed data, derived from the process module corresponding to the label latched, to the trace data storing part, and such that, when there is no abnormality detected, the monitoring part allows the DMA part to transfer the latched label to the trace data storing part.
摘要翻译： 固件跟踪数据获取方法构成为：根据来自监视部分的指示，提供用于监视固件处理的监视部分和用于将数据传送到跟踪数据存储部分的DMA部分，使得标签附于 存储在固件存储部分中的多个处理模块，并且使得激活的每个处理模块通知监视部分附接到其自身的标签。 监视部分锁定其通知的标签并监视相应处理的执行，使得当在执行期间检测到异常时，监视部分控制DMA部分，以便传送从处理模块导出的详细数据 对应于被锁定的标签到跟踪数据存储部分，并且使得当没有检测到异常时，监视部分允许DMA部分将锁存的标签传送到跟踪数据存储部分。
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5.发明授权公开(公告)号：US07304946B2
公开(公告)日：2007-12-04
申请号：US10108204
申请日：2002-03-27
IPC分类号： H04L12/26
摘要： A packet multiplexing control method and equipment using the method are realized by a simple control method with reduced hardware, enabling to provide low cost, efficient and fair bandwidth control corresponding to traffic characteristic of users. The packet multiplexing control method includes the steps of extracting a header part in each packet data received from a plurality of terminals; learning an address in the extracted header part; and controlling either admission processing or discard processing of the received packet according to the result of learning the address.
摘要翻译： 使用该方法的分组多路复用控制方法和设备通过简化的硬件减少控制方法来实现，能够提供与用户的流量特性相对应的低成本，高效且公平的带宽控制。 分组多路复用控制方法包括从多个终端接收的每个分组数据中提取报头部分的步骤; 在提取的头部中学习一个地址; 并且根据学习该地址的结果控制接收到的分组的接收处理或丢弃处理。
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6.发明授权Method and apparatus for selecting the oldest queued instructions without data dependencies 失效用于选择没有数据依赖性的最旧排队指令的方法和装置
公开(公告)号：US5745726A
公开(公告)日：1998-04-28
申请号：US523384
申请日：1995-09-05
申请人： Michael C. Shebanow , John Gmuender , Michael A. Simone , John R. F. S. Szeto , Takumi Maruyama , Deforest W. Tovey
发明人： Michael C. Shebanow , John Gmuender , Michael A. Simone , John R. F. S. Szeto , Takumi Maruyama , Deforest W. Tovey
CPC分类号： G06F9/3855 , G06F9/3836 , G06F9/3838 , G06F9/384
摘要： An instruction selector receives M instructions per clock cycle and stores N instructions in an instruction queue memory. An instruction queue generates a precedence matrix indicative of the age of the N instructions. A dependency checker determines the available registers for executing the instructions ready for execution. An oldest-instruction selector selects the M oldest instructions responsive to the precedence matrix and the eligible queue entry signals. The instruction queue provides the M selected instructions to execution units for execution. Upon completing the instructions, the execution units provide register availability signals to the dependency checker to release the registers used for the instructions.
摘要翻译： 指令选择器每个时钟周期接收M个指令，并将N个指令存储在指令队列存储器中。 指令队列产生指示N个指令的年龄的优先矩阵。 依赖关系检查器确定用于执行准备执行的指令的可用寄存器。 最古老的指令选择器响应于优先矩阵和符合条件的队列输入信号来选择M个最旧的指令。 指令队列将M个选择的指令提供给执行单元以供执行。 完成指令后，执行单元向依赖检查器提供寄存器可用性信号，以释放用于指令的寄存器。
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公开(公告)号：US5537535A
公开(公告)日：1996-07-16
申请号：US216141
申请日：1994-03-21
IPC分类号： G06F11/16 , G06F11/00 , G06F11/07 , G06F11/20 , G06F13/00 , G06F13/36 , G06F15/16 , G06F15/177
CPC分类号： G06F11/0796 , G06F11/0724 , G06F11/0745 , G06F11/0772
摘要： A multi-CPU system including a fault monitoring facility comprises a plurality of central processing units interconnected through a system bus and sending and receiving data through a plurality of bus interface units inserted in the system bus. A fault monitoring bus in parallel with the system bus is commonly accessed by the bus interface units. A bus interface unit which detects a fault notifies the other bus interface units simultaneously using the fault monitoring bus. Data-originating interface units and data-destination interface units receive fault information of the location and type of fault, which has occurred. Swift recovery from a faulty state is enabled.
摘要翻译： 包括故障监测设备的多CPU系统包括通过系统总线互连的多个中央处理单元，以及通过插入系统总线中的多个总线接口单元发送和接收数据。 与系统总线并联的故障监控总线通常由总线接口单元访问。 检测故障的总线接口单元使用故障监控总线同时通知其他总线接口单元。 数据发起接口单元和数据目的接口单元接收故障的位置和类型的故障信息。 从故障状态快速恢复已启用。
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公开(公告)号：US06654774B1
公开(公告)日：2003-11-25
申请号：US09670963
申请日：2000-09-26
IPC分类号： G06F501
CPC分类号： G06F5/01
摘要： A computer-implemented method and system for performing an arithmetic shift right by n of an m-bit negative number. A right shifter executes a logical shift right operation on the number to be shifted. A left shifter performs a left shift on an m-bit mask of ones, left shifting the mask by the one's complement of n. An OR operation is then performed on the results of the two shifting operations, producing the desired arithmetic shift right result.
摘要翻译： 一种计算机实现的方法和系统，用于以m位负号执行算术移位。 右移位器对要移位的号码执行逻辑换档操作。 左移位器在m位掩码上执行左移，左移使掩码乘以n的补码。 然后对两个移位操作的结果执行或运算，产生所需的算术移位右结果。
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