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    Shifted segment layout for differential signal traces to mitigate bundle weave effect
    1.
    发明申请
    Shifted segment layout for differential signal traces to mitigate bundle weave effect 有权
    用于差分信号迹线的变换段布局，以减轻束编织效应

    公开(公告)号：US20070223205A1

    公开(公告)日：2007-09-27

    申请号：US11385093

    申请日：2006-03-21

    申请人： Tao Liang ,  Stephen Hall ,  Howard Heck ,  Gary Brist ,  Bryce Horine

    发明人： Tao Liang ,  Stephen Hall ,  Howard Heck ,  Gary Brist ,  Bryce Horine

    IPC分类号： H05K7/00

    CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

    摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

    摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

    Shifted segment layout for differential signal traces to mitigate bundle weave effect
    4.
    发明授权
    Shifted segment layout for differential signal traces to mitigate bundle weave effect 有权
    用于差分信号迹线的变换段布局，以减轻束编织效应

    公开(公告)号：US07977581B2

    公开(公告)日：2011-07-12

    申请号：US12757356

    申请日：2010-04-09

    申请人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    发明人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    IPC分类号： H05K1/16

    CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

    摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

    摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

    Shifted segment layout for differential signal traces to mitigate bundle weave effect
    5.
    发明授权
    Shifted segment layout for differential signal traces to mitigate bundle weave effect 有权
    用于差分信号迹线的变换段布局，以减轻束编织效应

    公开(公告)号：US07723618B2

    公开(公告)日：2010-05-25

    申请号：US12193298

    申请日：2008-08-18

    申请人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    发明人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    IPC分类号： H05K1/03

    CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

    摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

    摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

    SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE BUNDLE WEAVE EFFECT
    6.
    发明申请
    SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE BUNDLE WEAVE EFFECT 有权
    用于不同信号的移位部分布局以缓解整体效果

    公开(公告)号：US20100202118A1

    公开(公告)日：2010-08-12

    申请号：US12757356

    申请日：2010-04-09

    申请人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    发明人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    IPC分类号： H05K1/18

    CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

    摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

    摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

    SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE BUNDLE WEAVE EFFECT
    7.
    发明申请
    SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE BUNDLE WEAVE EFFECT 有权
    用于不同信号的移位部分布局以缓解整体效果

    公开(公告)号：US20080308306A1

    公开(公告)日：2008-12-18

    申请号：US12193298

    申请日：2008-08-18

    申请人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    发明人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    IPC分类号： H05K1/03

    CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

    摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

    摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

    Shifted segment layout for differential signal traces to mitigate bundle weave effect
    8.
    发明授权
    Shifted segment layout for differential signal traces to mitigate bundle weave effect 有权
    用于差分信号迹线的变换段布局，以减轻束编织效应

    公开(公告)号：US07427719B2

    公开(公告)日：2008-09-23

    申请号：US11385093

    申请日：2006-03-21

    申请人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    发明人： Tao Liang ,  Stephen H. Hall ,  Howard Heck ,  Gary A. Brist ,  Bryce Horine

    IPC分类号： H05K1/03

    CPC分类号： H05K1/0245 ,  H05K1/0366 ,  H05K2201/029 ,  H05K2201/09236

    摘要： An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis.

    摘要翻译： 制造品包括电路板和电路板上或电路板中的一对迹线。 该对轨迹包括第一轨迹和第二轨迹。 第一迹线包括连续地连接到第一段的第一段和第二段。 第一段与第一纵向轴线重合。 第二个跟踪包括与第一个跟踪的第一个段一起运行的第一个段。 第二轨迹还包括与第一轨迹的第二段一起运行的第二段。 第二迹线的第二段连续地连接到第二迹线的第一段。 第二轨迹的第二段与第一纵向轴线重合。

    Method and system for implementing time synchronization in local area network (LAN)
    9.
    发明授权
    Method and system for implementing time synchronization in local area network (LAN) 有权
    在局域网（LAN）中实现时间同步的方法和系统

    公开(公告)号：US08705578B2

    公开(公告)日：2014-04-22

    申请号：US13497693

    申请日：2010-06-29

    申请人： Yanbin Fang ,  Tao Liang

    发明人： Yanbin Fang ,  Tao Liang

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0664 ,  G04R20/06

    摘要： A method and a system for implementing time synchronization in a local area network are disclosed, and the local area network includes a master system device (1) and a slave system device (31, 32, 33). The method includes: the master system device (1) synchronizing a local time according to a Universal Time Coordinated (UTC) time normally received from a Global Positioning System (GPS) satellite and a network clock aligned with the UTC time, and regularly broadcasting the local time to each network node which serves as the slave system device (31, 32, 33) and needs to perform time synchronization; and the slave system device (31, 32, 33) synchronously updating the local time according to the received local time of the maser system device (1) and a local network clock aligned with the network clock of the maser system device (1).

    摘要翻译： 公开了一种用于在局域网中实现时间同步的方法和系统，并且局域网包括主系统设备（1）和从系统设备（31,32,33）。 该方法包括：主系统设备（1）根据从全球定位系统（GPS）卫星正常接收的通用时间协调（UTC）时间和与UTC时间对齐的网络时钟同步本地时间，并且定期地广播 用于作为从系统设备（31,32,33）的每个网络节点的本地时间，并且需要执行时间同步; 并且所述从系统设备（31,32,33）根据所述主机系统设备（1）的接收到的本地时间和与所述主系统设备（1）的网络时钟对准的本地网络时钟同步地更新所述本地时间。

    Method and System for Implementing Time Synchronization in Local Area Network (LAN)
    10.
    发明申请
    Method and System for Implementing Time Synchronization in Local Area Network (LAN) 有权
    在局域网（LAN）中实现时间同步的方法和系统

    公开(公告)号：US20120294318A1

    公开(公告)日：2012-11-22

    申请号：US13497693

    申请日：2010-06-29

    申请人： Yanbin Fang ,  Tao Liang

    发明人： Yanbin Fang ,  Tao Liang

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0664 ,  G04R20/06

    摘要： A method and a system for implementing time synchronization in a local area network are disclosed, and the local area network includes a master system device (1) and a slave system device (31, 32, 33). The method includes: the master system device (1) synchronizing a local time according to a Universal Time Coordinated (UTC) time normally received from a Global Positioning System (GPS) satellite and a network clock aligned with the UTC time, and regularly broadcasting the local time to each network node which serves as the slave system device (31, 32, 33) and needs to perform time synchronization; and the slave system device (31, 32, 33) synchronously updating the local time according to the received local time of the maser system device (1) and a local network clock aligned with the network clock of the maser system device (1).

    摘要翻译： 公开了一种用于在局域网中实现时间同步的方法和系统，并且局域网包括主系统设备（1）和从系统设备（31,32,33）。 该方法包括：主系统设备（1）根据从全球定位系统（GPS）卫星正常接收的通用时间协调（UTC）时间和与UTC时间对齐的网络时钟同步本地时间，并且定期地广播 用于作为从系统设备（31,32,33）的每个网络节点的本地时间，并且需要执行时间同步; 并且所述从系统设备（31,32,33）根据所述主机系统设备（1）的接收到的本地时间和与所述主系统设备（1）的网络时钟对准的本地网络时钟同步地更新所述本地时间。