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1.发明授权Semiconductor device with improved insulating film and floating gate arrangement to decrease memory cell size without reduction of capacitance 有权具有改进的绝缘膜和浮栅布置的半导体器件，以减小存储器单元尺寸而不降低电容公开(公告)号：US08212305B2
公开(公告)日：2012-07-03
申请号：US12633815
申请日：2009-12-09
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US20110284945A1
公开(公告)日：2011-11-24
申请号：US13195068
申请日：2011-08-01
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US20080179653A1
公开(公告)日：2008-07-31
申请号：US11936339
申请日：2007-11-07
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US08466507B2
公开(公告)日：2013-06-18
申请号：US13195068
申请日：2011-08-01
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US20100084701A1
公开(公告)日：2010-04-08
申请号：US12633815
申请日：2009-12-09
IPC分类号： H01L27/115
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US07312123B2
公开(公告)日：2007-12-25
申请号：US11240375
申请日：2005-10-03
IPC分类号： H01L21/336
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US07064380B2
公开(公告)日：2006-06-20
申请号：US10902141
申请日：2004-07-30
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
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公开(公告)号：US20050051832A1
公开(公告)日：2005-03-10
申请号：US10902141
申请日：2004-07-30
IPC分类号： H01L27/10 , G11C16/04 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/76 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US07662686B2
公开(公告)日：2010-02-16
申请号：US11936339
申请日：2007-11-07
IPC分类号： H01L21/336
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
摘要翻译： 具有非易失性存储器的半导体器件的尺寸减小。 在具有多个非易失性存储单元的AND型闪速存储器中，具有多个第一电极，与之交叉的多个字线，以及设置在分别位于多个相邻的第一电极之间且重叠的位置的多个浮置栅电极 如平面图所示，多个字线如横截面那样形成为凸形，从而高于第一电极。 结果，即使非易失性存储单元的尺寸减小，也可以容易地处理浮置栅电极。 此外，可以提高字线的浮栅电极和控制栅电极之间的耦合比，而不增加非易失存储单元所占的面积。
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公开(公告)号：US20060022257A1
公开(公告)日：2006-02-02
申请号：US11240375
申请日：2005-10-03
IPC分类号： H01L29/788
CPC分类号： H01L27/11517 , G11C16/0433 , H01L21/32053 , H01L21/32055 , H01L21/768 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42376
摘要： A semiconductor device having a nonvolatile memory is reduced in size. In an AND type flash memory having a plurality of nonvolatile memory cells having a plurality of first electrodes, a plurality of word lines crossing therewith, and a plurality of floating gate electrodes disposed at positions which respectively lie between the plurality of adjacent first electrodes and overlap the plurality of word lines, as seen in plan view, the plurality of floating gate electrodes are formed in a convex shape, as seen in cross section, so as to be higher than the first electrodes. As a result, even when nonvolatile memory cells are reduced in size, it is possible to process the floating gate electrodes with ease. In addition, it is possible to improve the coupling ratio between floating gate electrodes and control gate electrodes of the word lines without increasing the area occupied by the nonvolatile memory cells.
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