公开(公告)号：US20080195732A1

公开(公告)日：2008-08-14

申请号：US12019231

申请日：2008-01-24

申请人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Hideaki Suzuki ,  Norihisa Yanagihara ,  Makiko Naemura

发明人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Hideaki Suzuki ,  Norihisa Yanagihara ,  Makiko Naemura

IPC分类号： G06F15/173

CPC分类号： H04L67/325 ,  H04L12/2818 ,  H04L12/2856 ,  H04L29/06 ,  H04L43/00 ,  H04L63/1458 ,  H04L69/40

摘要： An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.

摘要翻译： 本文所公开的信息处理器防止由于来自网络的入站业务超出业务状态（在DoS攻击下）时极端频繁的接收处理对较高优先级处理的不利影响。 附加到网络的信息处理器收集关于流量状态的信息，并且如果确定存在过流量状态，则由于与数据处理块的通信而不通过中断请求而停止通信处理功能。 在这种状态下，信息处理器继续收集关于业务状态的信息，并且当确定过流量状态已经终止时，开始将中断请求传送到数据处理块，并使通信处理功能恢复。

公开(公告)号：US07814224B2

公开(公告)日：2010-10-12

申请号：US12019231

申请日：2008-01-24

申请人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Hideaki Suzuki ,  Norihisa Yanagihara ,  Makiko Naemura

发明人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Hideaki Suzuki ,  Norihisa Yanagihara ,  Makiko Naemura

IPC分类号： G06F15/16

CPC分类号： H04L67/325 ,  H04L12/2818 ,  H04L12/2856 ,  H04L29/06 ,  H04L43/00 ,  H04L63/1458 ,  H04L69/40

摘要： An information processor disclosed herein prevents adverse impacts on higher priority processing due to extremely frequent receive processing when inbound traffic from a network is over-traffic state (under a DoS attack). The information processor attached to a network collects information about traffic state and, if it is determined that over-traffic state is present, deactivates the communication processing function without passing an interrupt request due to communication to the data processing block. In this state, the information processor continues to collect information about traffic state and, when it is determined that over-traffic state has terminated, starts to transfer an interrupt request to the data processing block and makes the communication processing function recover.

摘要翻译： 本文所公开的信息处理器防止由于来自网络的入站业务超出业务状态（在DoS攻击下）时极端频繁的接收处理对较高优先级处理的不利影响。 附加到网络的信息处理器收集关于流量状态的信息，并且如果确定存在过流量状态，则由于与数据处理块的通信而不通过中断请求而停止通信处理功能。 在这种状态下，信息处理器继续收集关于业务状态的信息，并且当确定过流量状态已经终止时，开始将中断请求传送到数据处理块，并使通信处理功能恢复。

公开(公告)号：US20070112983A1

公开(公告)日：2007-05-17

申请号：US11599383

申请日：2006-11-15

申请人： Tsutomu Yamada ,  Hiromichi Endoh ,  Noritaka Matsumoto ,  Satoru Funaki ,  Tatsuya Maruyama ,  Atsushi Ito ,  Fumiyuki Tamura ,  Norihisa Yanagihara ,  Makiko Naemura

发明人： Tsutomu Yamada ,  Hiromichi Endoh ,  Noritaka Matsumoto ,  Satoru Funaki ,  Tatsuya Maruyama ,  Atsushi Ito ,  Fumiyuki Tamura ,  Norihisa Yanagihara ,  Makiko Naemura

IPC分类号： G06F13/00

CPC分类号： G06F13/37

摘要： A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.

摘要翻译： 一种作为堆叠总线系统的计算机系统，其中多个计算机模块彼此堆叠并彼此连接并且能够自动匹配和分配诸如时钟和中断的总线资源。 在包括一个系统模块和n个外围模块的计算机系统中，每个外围模块包括中断选择器，时钟选择器，仲裁信号选择器，资源判定单元和位置识别单元。 所述位置识别单元与存在于所述系统模块中的位置配置单元配合，以在所述计算机系统中识别包括所述位置识别单元的模块的位置，并且自主地决定所述模块使用的总线资源。 通过允许中断选择器，时钟选择器和仲裁信号选择器来选择和使用所决定的总线资源，每个外围模块可以匹配和配置计算机系统中的总线资源。

公开(公告)号：US07716405B2

公开(公告)日：2010-05-11

申请号：US11599383

申请日：2006-11-15

申请人： Tsutomu Yamada ,  Hiromichi Endoh ,  Noritaka Matsumoto ,  Satoru Funaki ,  Tatsuya Maruyama ,  Atsushi Ito ,  Fumiyuki Tamura ,  Norihisa Yanagihara ,  Makiko Naemura

发明人： Tsutomu Yamada ,  Hiromichi Endoh ,  Noritaka Matsumoto ,  Satoru Funaki ,  Tatsuya Maruyama ,  Atsushi Ito ,  Fumiyuki Tamura ,  Norihisa Yanagihara ,  Makiko Naemura

IPC分类号： G06F13/36

CPC分类号： G06F13/37

摘要： A computer system, being a stack bus system in which a plurality of computer modules are stacked and connected to one another and being capable of automatically matching and allocating bus resources such as clocks and interrupts, is provided. In the computer system including one system module and n peripheral modules, each peripheral module includes an interrupt selector, a clock selector, an arbitration signal selector, a resource decision unit, and a position identification unit. The position identification unit cooperates with a position configuration unit present in the system module to identify a position of the module, which includes the position identification unit, in the computer system, and autonomously decides bus resources used by the module. By allowing the interrupt selector, the clock selector, and the arbitration signal selector to select and use the decided bus resources, each peripheral module can match and configure the bus resources in the computer system.

摘要翻译： 一种作为堆叠总线系统的计算机系统，其中多个计算机模块彼此堆叠并彼此连接并且能够自动匹配和分配诸如时钟和中断的总线资源。 在包括一个系统模块和n个外围模块的计算机系统中，每个外围模块包括中断选择器，时钟选择器，仲裁信号选择器，资源判定单元和位置识别单元。 所述位置识别单元与存在于所述系统模块中的位置配置单元配合，以在所述计算机系统中识别包括所述位置识别单元的模块的位置，并且自主地决定所述模块使用的总线资源。 通过允许中断选择器，时钟选择器和仲裁信号选择器来选择和使用所决定的总线资源，每个外围模块可以匹配和配置计算机系统中的总线资源。

公开(公告)号：US07861115B2

公开(公告)日：2010-12-28

申请号：US12215063

申请日：2008-06-24

申请人： Norihisa Yanagihara ,  Hajime Kihara ,  Tsutomu Yamada ,  Makiko Naemura ,  Kenji Seino

发明人： Norihisa Yanagihara ,  Hajime Kihara ,  Tsutomu Yamada ,  Makiko Naemura ,  Kenji Seino

IPC分类号： G06F11/00

CPC分类号： G06F1/24 ,  G06F11/0724 ,  G06F11/0793

摘要： To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.

摘要翻译： 为了在异常状态下仅复位组件中的CPU而不影响正常状态下的组件的CPU，其中每个至少包括CPU的多个组件通过公共总线相互连接的多组件系统， 包括：第一复位信号生成单元，其通过开关操作产生复位信号，以将复位信号发送到各个组件;以及判断单元，其设置在每个组件中，以确定是否允许CPU的复位。 如果CPU处于正常状态，则判断单元禁止CPU根据复位信号进行复位，并且如果CPU处于异常状态，CPU会响应复位信号复位。

公开(公告)号：US20090013221A1

公开(公告)日：2009-01-08

申请号：US12215063

申请日：2008-06-24

申请人： Norihisa Yanagihara ,  Hajime Kihara ,  Tsutomu Yamada ,  Makiko Naemura ,  Kenji Seino

发明人： Norihisa Yanagihara ,  Hajime Kihara ,  Tsutomu Yamada ,  Makiko Naemura ,  Kenji Seino

IPC分类号： G06F11/08

CPC分类号： G06F1/24 ,  G06F11/0724 ,  G06F11/0793

摘要： To reset only the CPU in a component in an abnormal condition without affecting CPUs of components in a normal condition, a multi-component system, in which a plurality of components each including at least a CPU are connected via a common bus to each other, includes a first reset signal generating unit which generates a reset signal by a switch operation to send the reset signal to respective components and a judge unit which is disposed in each component to determine whether or not resetting of a CPU is allowed. The judge unit inhibits, if the CPU is in a normal condition, the resetting of the CPU in response to the reset signal and resets, if the CPU is in an abnormal condition, the CPU in response to the reset signal.

摘要翻译： 为了在异常状态下仅复位组件中的CPU而不影响正常状态下的组件的CPU，其中每个至少包括CPU的多个组件通过公共总线相互连接的多组件系统， 包括：第一复位信号生成单元，其通过开关操作产生复位信号，以将复位信号发送到各个组件;以及判断单元，其设置在每个组件中，以确定是否允许CPU的复位。 如果CPU处于正常状态，则判断单元禁止CPU根据复位信号进行复位，并且如果CPU处于异常状态，CPU会响应复位信号复位。

公开(公告)号：US08788735B2

公开(公告)日：2014-07-22

申请号：US12544347

申请日：2009-08-20

申请人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hiroshi Fujii

发明人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hiroshi Fujii

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812

摘要： An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.

摘要翻译： 中断控制单元基于发送到受控对象或从控制对象接收到的分组来提供对从加速器到CPU的中断的控制。 中断控制单元包括：存储部分，用于在其中存储中断控制定时表，其中描述了切换中断控制的模式的条件; 以及中断控制模式切换部分，用于根据存储部分中的中断控制定时表将中断控制模式切换到许可模式和掩模模式之间的CPU。

公开(公告)号：US20100070668A1

公开(公告)日：2010-03-18

申请号：US12544347

申请日：2009-08-20

申请人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hiroshi Fujii

发明人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hiroshi Fujii

IPC分类号： G06F13/24

CPC分类号： G06F13/24 ,  G06F9/4812

摘要： An interrupt control unit provides controls on an interrupt from an accelerator to a CPU based on a packet transmitted to or received from a controlled object. The interrupt control unit includes: a storage part for storing therein an interrupt control timing table in which a condition of switching a mode of the interrupt control is described; and an interrupt control mode switching part for switching the mode of the interrupt control to the CPU between a permission mode and a mask mode, based on the interrupt control timing table in the storage part.

摘要翻译： 中断控制单元基于发送到受控对象或从控制对象接收到的分组来提供对从加速器到CPU的中断的控制。 中断控制单元包括：存储部分，用于在其中存储中断控制定时表，其中描述了切换中断控制的模式的条件; 以及中断控制模式切换部分，用于根据存储部分中的中断控制定时表将中断控制模式切换到许可模式和掩模模式之间的CPU。

公开(公告)号：US09148297B2

公开(公告)日：2015-09-29

申请号：US13030272

申请日：2011-02-18

申请人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hironori Ohashi ,  Yutaka Matsumoto

发明人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hironori Ohashi ,  Yutaka Matsumoto

IPC分类号： G01R31/08 ,  H04L12/40 ,  H04L12/413 ,  H04L12/437

CPC分类号： H04L12/40176 ,  H04L12/413 ,  H04L12/437

摘要： An information processor capable of ensuring time synchronization accuracy, ensuring EtherCAT command consistency, and easily developing the software based on a 2-port configuration even when a communication path error occurs includes: an arithmetic section; at least two communication sections each including a transmission section and a reception section; and a redundant communication control section that controls a communication path between the arithmetic section and the communication section. The redundant communication control section includes: a communication path state determination section that determines a network path state; and a redundant path switching section that switches connection between the arithmetic section and at least two communication sections.

摘要翻译： 一种信息处理器，能够确保时间同步精度，确保EtherCAT命令一致性，并且即使发生通信路径错误，也可以容易地开发基于2端口配置的软件，包括：运算部分; 至少两个通信部分，每个通信部分包括传输部分和接收部分; 以及控制运算部和通信部之间的通信路径的冗余通信控制部。 冗余通信控制部分包括：通信路径状态确定部分，其确定网络路径状态; 以及冗余路径切换部，切换运算部与至少两个通信部之间的连接。

公开(公告)号：US20110205886A1

公开(公告)日：2011-08-25

申请号：US13030272

申请日：2011-02-18

申请人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hironori Ohashi ,  Yutaka Matsumoto

发明人： Tatsuya Maruyama ,  Tsutomu Yamada ,  Norihisa Yanagihara ,  Shinji Yonemoto ,  Takashi Iwaki ,  Hironori Ohashi ,  Yutaka Matsumoto

IPC分类号： H04L1/00

CPC分类号： H04L12/40176 ,  H04L12/413 ,  H04L12/437

摘要： An information processor capable of ensuring time synchronization accuracy, ensuring EtherCAT command consistency, and easily developing the software based on a 2-port configuration even when a communication path error occurs includes: an arithmetic section; at least two communication sections each including a transmission section and a reception section; and a redundant communication control section that controls a communication path between the arithmetic section and the communication section. The redundant communication control section includes: a communication path state determination section that determines a network path state; and a redundant path switching section that switches connection between the arithmetic section and at least two communication sections. The network provides a logical ring topology for a packet communication path. The redundant path switching section functions based on the communication path state determined by the communication path state determination section and changes a connection path between the communication sections and a communication path between the communication section and the arithmetic section.

摘要翻译： 一种信息处理器，能够确保时间同步精度，确保EtherCAT命令一致性，并且即使发生通信路径错误，也可以容易地开发基于2端口配置的软件，包括：运算部分; 至少两个通信部分，每个通信部分包括传输部分和接收部分; 以及控制运算部和通信部之间的通信路径的冗余通信控制部。 冗余通信控制部分包括：通信路径状态确定部分，其确定网络路径状态; 以及冗余路径切换部，切换运算部与至少两个通信部之间的连接。 网络为分组通信路径提供逻辑环形拓扑。 冗余路径切换部基于由通信路径状态判定部确定的通信路径状态起作用，并且改变通信部之间的连接路径与通信部与运算部之间的通信路径。