公开(公告)号：US20050236703A1

公开(公告)日：2005-10-27

申请号：US10830910

申请日：2004-04-22

申请人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： G01R31/30 ,  G01R31/3185 ,  H01L23/02

CPC分类号： G01R31/3008 ,  G01R31/318505 ,  G01R31/318533

摘要： A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

摘要翻译： 主模具和堆叠模具包括在相同的组件封装中。 在主管芯上实现传输门（370），并且能够在主管芯和堆叠管芯之间的连接（318）中接收泄漏电流，并将泄漏电流传导到接合焊盘（344） 可以在包装外部访问。 因此，可以在封装模具之后测试主模具和堆叠模具之间的连接性。 传输门在高速测试和正常运行期间被禁用。 封装还可以包括多路复用器（364），其在高速测试期间被启用以在封装级别输入和输出测试信号。 方向信号用于指示测试信号是否被输入到主模具或从主模块输出。

公开(公告)号：US20060214276A1

公开(公告)日：2006-09-28

申请号：US11436452

申请日：2006-05-18

申请人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H01L23/02

CPC分类号： G01R31/3008 ,  G01R31/318505 ,  G01R31/318533

摘要： A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

摘要翻译： 主模具和堆叠模具包括在相同的组件封装中。 在主管芯上实现传输门（370），并且能够在主管芯和堆叠管芯之间的连接（318）中接收泄漏电流，并将泄漏电流传导到接合焊盘（344） 可以在包装外部访问。 因此，可以在封装模具之后测试主模具和堆叠模具之间的连接性。 传输门在高速测试和正常运行期间被禁用。 封装还可以包括多路复用器（364），其在高速测试期间被启用以在封装级别输入和输出测试信号。 方向信号用于指示测试信号是否被输入到主模具或从主模块输出。

公开(公告)号：US07772831B2

公开(公告)日：2010-08-10

申请号：US11436452

申请日：2006-05-18

申请人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H01L23/02 ,  G01R31/26

CPC分类号： G01R31/3008 ,  G01R31/318505 ,  G01R31/318533

摘要： A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

摘要翻译： 主模具和堆叠模具包括在相同的组件封装中。 在主管芯上实现传输门（370），并且能够在主管芯和堆叠管芯之间的连接（318）中接收泄漏电流，并将泄漏电流传导到接合焊盘（344） 可以在包装外部访问。 因此，可以在封装模具之后测试主模具和堆叠模具之间的连接性。 传输门在高速测试和正常运行期间被禁用。 封装还可以包括多路复用器（364），其在高速测试期间被启用以在封装级别输入和输出测试信号。 方向信号用于指示测试信号是否被输入到主模具或从主模块输出。

公开(公告)号：US07075175B2

公开(公告)日：2006-07-11

申请号：US10830910

申请日：2004-04-22

申请人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Tauseef Kazi ,  Jeff Gemar ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H01L23/02

CPC分类号： G01R31/3008 ,  G01R31/318505 ,  G01R31/318533

摘要： A main die and a stacked die are included in the same component package. A transmission gate (370) is implemented on the main die, and can be enabled to receive leakage current in a connection (318) between the main die and the stacked die, and to conduct the leakage current to a bonding pad (344) that is accessible external to the package. Thus, the connectivity between the main die and the stacked die can be tested after the dies are packaged. The transmission gate is disabled during high-speed testing and normal operation. The package can also include a multiplexer (364) that is enabled during high-speed testing to input and output test signals at the package level. A direction signal is used to indicate whether test signals are being input to or output from the main die.

公开(公告)号：US08138814B2

公开(公告)日：2012-03-20

申请号：US12181655

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03L5/00

CPC分类号： H03K19/00315 ,  H03K19/017581 ,  H03K19/018507

摘要： A signal driver for an interface circuit has a first stage level shifter to accept input signals and output signals at a first signal level. The signal driver also has a second stage level shifter coupled to the first stage level shifter to output signals at a second signal level. Electronic components of the first and second stage level shifter have reliability limits less than the second signal level. The first and second stage configurations of the first stage level shifter and the second stage level shifter prevents exposing the electronic components to terminal to terminal signal levels higher than the reliability limits when processing signals for output at the second signal level.

摘要翻译： 用于接口电路的信号驱动器具有第一级电平移位器，以接收输入信号并以第一信号电平输出信号。 信号驱动器还具有耦合到第一级电平移位器的第二级电平移位器，以在第二信号电平输出信号。 第一级和第二级电平移位器的电子部件具有小于第二信号电平的可靠性限制。 第一级电平移位器和第二级电平转换器的第一和第二级配置防止当处理用于在第二信号电平输出的信号时将电子部件暴露于高于可靠性限制的端对端信号电平。

公开(公告)号：US07843234B2

公开(公告)日：2010-11-30

申请号：US10825481

申请日：2004-04-14

申请人： Vaishnav Srinivas ,  Vivek Mohan

发明人： Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K19/0013 ,  H03K3/356113 ,  H03K17/08122

摘要： A break-before-make predriver for disabling a PFET of an output driver before enabling an NFET, and vice versa. The predriver includes an input inverter, two cross-coupled inverters, and output buffers. The predriver provides enhanced break-before-make action through sizing the NFETs larger than the PFETs in the predriver's cross-coupled inverters. The input inverter, the cross-coupled inverters and the first and second output buffers are sized with respect to each other such that substantially equal break before make action is provided on both rising and falling edges. The predriver also includes level-shifting capabilities through a different voltage supply at the PFETs of the cross-coupled inverter. The predriver also includes two data output nodes for connection to the two inputs of an output driver. The predriver provides for tristate action by disabling the signal from the predriver output nodes.

摘要翻译： 用于在启用NFET之前禁用输出驱动器的PFET的前置制造预驱动器，反之亦然。 预驱动器包括输入反相器，两个交叉耦合的反相器和输出缓冲器。 预驱动器通过将大于预驱动器交叉耦合逆变器中的PFET的NFET尺寸进行调整，从而提供增强的“先行后制”动作。 输入反相器，交叉耦合反相器和第一和第二输出缓冲器相对于彼此大小，使得在上升沿和下降沿两者之间提供在作用之前基本相等的断开。 预驱动器还包括通过交叉耦合逆变器的PFET处的不同电压源的电平转换能力。 预驱动器还包括用于连接到输出驱动器的两个输入的两个数据输出节点。 预驱动器通过禁用来自预驱动输出节点的信号来提供三态动作。

公开(公告)号：US07804334B2

公开(公告)日：2010-09-28

申请号：US12181633

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03K5/22

CPC分类号： H03K19/018507 ,  G01R19/16519 ,  G01R19/16552 ,  H03K19/00315

摘要： A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.

摘要翻译： 电平检测器具有适于接收用于检测特定电平的多个信号电平的信号的输入电路。 信号电平包括第一信号电平和较大的第二信号电平。 输入电路的电子元件具有小于第二信号电平的可靠性水平。 锁存电路耦合到输入电路，用于锁存与所接收信号的检测电平一致的信号。

公开(公告)号：US07768299B2

公开(公告)日：2010-08-03

申请号：US11832128

申请日：2007-08-01

申请人： Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03K19/0175

CPC分类号： H03K19/018592 ,  H03K19/00384

摘要： Methods and apparatuses are presented for voltage tolerant floating N-well circuits. An apparatus for mitigating leakage currents caused by input voltages is presented which includes a first transistor having a source coupled to a positive voltage supply, and a drain coupled to a floating node. The apparatus may further include a controllable pull-down path coupled to a negative voltage supply and the first transistor, wherein the controllable pull-down path is configured to turn on the first transistor and pull-up the floating node during a first state. The apparatus may further include a second transistor having a source coupled to a gate of the first transistor, and drain coupled to the floating node, wherein the second transistor is configured to place the floating node at a floating potential during a second state.

摘要翻译： 提出了用于耐压漂浮N阱电路的方法和装置。 提供了一种用于减轻由输入电压引起的漏电流的装置，其包括具有耦合到正电压源的源极和耦合到浮动节点的漏极的第一晶体管。 该装置还可以包括耦合到负电压源和第一晶体管的可控下拉通路，其中可控下拉通道被配置为在第一状态期间导通第一晶体管并上拉浮动节点。 该装置还可以包括具有耦合到第一晶体管的栅极的源极和耦合到浮动节点的漏极的第二晶体管，其中第二晶体管被配置为在第二状态期间将浮动节点置于浮动电位。

公开(公告)号：US20100026362A1

公开(公告)日：2010-02-04

申请号：US12181633

申请日：2008-07-29

申请人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

发明人： Vijay Shankar ,  Abheek Gupta ,  Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03L5/00

CPC分类号： H03K19/018507 ,  G01R19/16519 ,  G01R19/16552 ,  H03K19/00315

摘要： A level detector has an input circuit adapted to accept signals of multiple signal levels for detecting a specific level. The signal levels include a first signal level and a larger second signal level. Electronic components of the input circuit have reliability levels less than the second signal level. A latch circuit is coupled to the input circuit for latching a signal consistent with a detected level of an accepted signal.

摘要翻译： 电平检测器具有适于接收用于检测特定电平的多个信号电平的信号的输入电路。 信号电平包括第一信号电平和较大的第二信号电平。 输入电路的电子元件具有小于第二信号电平的可靠性水平。 锁存电路耦合到输入电路，用于锁存与所接收信号的检测电平一致的信号。

公开(公告)号：US07605618B2

公开(公告)日：2009-10-20

申请号：US11332118

申请日：2006-01-12

申请人： Vaishnav Srinivas ,  Vivek Mohan

发明人： Vaishnav Srinivas ,  Vivek Mohan

IPC分类号： H03B1/00

CPC分类号： H03K3/356104

摘要： A digital output driver includes a pre-driver and a driver that may be implemented with thin-oxide FETs. The pre-driver generates first and second digital signals based on a digital input signal. The first digital signal has a first voltage range determined by a first (e.g., pad) supply voltage and an intermediate voltage. The second digital signal has a second voltage range determined by a second (e.g., core) supply voltage and circuit ground. The driver receives the first and second digital signals and provides a digital output signal having a third voltage range determined by the first supply voltage and circuit ground. The pre-driver may include a latch and a latch driver. The latch stores the current logic value for the digital input signal. The latch driver writes the logic value to the latch. The latch driver is enabled for a short time duration to write the logic value and is turned off afterward.

摘要翻译： 数字输出驱动器包括可以用薄氧化物FET实现的预驱动器和驱动器。 预驱动器基于数字输入信号产生第一和第二数字信号。 第一数字信号具有由第一（例如，焊盘）电源电压和中间电压确定的第一电压范围。 第二数字信号具有由第二（例如，核心）电源电压和电路接地确定的第二电压范围。 驱动器接收第一和第二数字信号，并提供具有由第一电源电压和电路接地确定的第三电压范围的数字输出信号。 预驱动器可以包括锁存器和锁存器驱动器。 锁存器存储数字输入信号的当前逻辑值。 锁存驱动器将逻辑值写入锁存器。 锁存驱动器在短时间内被使能以写入逻辑值，之后被关闭。