公开(公告)号：US07478307B1

公开(公告)日：2009-01-13

申请号：US11133056

申请日：2005-05-19

申请人： Tayung Wong ,  Kenneth J. Gibbons ,  Neil N. Duncan

发明人： Tayung Wong ,  Kenneth J. Gibbons ,  Neil N. Duncan

IPC分类号： G11C29/00

CPC分类号： G06F11/1044 ,  G11C5/04 ,  G11C2029/0411

摘要： A system and method for storing error correction check words in computer memory modules. Check bits stored within a given word line in a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from the failure of a word line will appear as single-bit errors to an error correction subsystem.

摘要翻译： 一种用于在计算机存储器模块中存储纠错检查词的系统和方法。 存储在动态随机存取存储器（DRAM）芯片中的给定字线内的位的检查被分配给不同的检查字。 通过以这种方式分配校验位来检查字，由字线故障引起的多位软错误将作为纠错子系统的单位错误出现。

公开(公告)号：US06961281B2

公开(公告)日：2005-11-01

申请号：US10661872

申请日：2003-09-12

申请人： Tayung Wong ,  Clement C. Fang ,  David J. Jeffrey ,  Neil N. Duncan

发明人： Tayung Wong ,  Clement C. Fang ,  David J. Jeffrey ,  Neil N. Duncan

IPC分类号： G06F12/06 ,  G06F13/42 ,  G11C5/04 ,  G11C8/00 ,  G11C8/12

CPC分类号： G06F13/4243 ,  G06F12/0653 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory module for use in a two rank memory module system includes a plurality of memory devices and a control circuit. In one embodiment, the control circuit may be configured to generate a chip select signal that is provided to each of the memory devices. The chip select signal may be dependent upon assertions of a first bank chip select signal and a second bank chip select signal received from a memory controller. The control circuit may be further configured to generate an address signal that is provided to each of the memory devices. The address signal may be asserted dependent upon which of the first bank chip select signal and the second bank chip select signal are asserted.