Methods and nodes for handling memory

    公开(公告)号:US11714753B2

    公开(公告)日:2023-08-01

    申请号:US17309657

    申请日:2018-12-13

    IPC分类号: G06F12/0806

    CPC分类号: G06F12/0806 G06F2212/62

    摘要: A method in a multi-core processing system which comprises a processor comprising at least a first and a second processing unit, a cache, common to the first and the second processing unit, comprising a first cache portion associated with the first processing unit and a second cache portion associated with the second processing unit, a memory, comprising a first memory portion associated with the first cache portion and a second memory portion associated with the second cache portion. The method comprises detecting that a data access criteria of the second memory portion is fulfilled, establishing that first data stored in the second memory portion is related to a first application running on the first processing unit, allocating at least a part of the first memory portion to the first application based on cache information, and migrating the first data to the part of first memory portion.