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公开(公告)号：US20240223834A1
公开(公告)日：2024-07-04
申请号：US18557325
申请日：2021-04-30
发明人： Fredrik Dahlgren , Alexander Hunt , Gang Zou , Sunny Sharma , Florent Torres
IPC分类号： H04N21/2668 , H04N13/30 , H04N13/337 , H04N13/341 , H04N13/344 , H04N21/41
CPC分类号： H04N21/2668 , H04N13/337 , H04N13/341 , H04N13/344 , H04N21/4104 , H04N2013/40
摘要： A media distribution management unit (10) for providing multi-content media to one or more users (2a, 2b, . . . , 2x) is disclosed. The media distribution management unit (10) is configured to: map, in accordance with a respective profile of one or more users (2a, 2b, . . . , 2x), alternative content into a first media stream (S1) comprising main content, and to playback the first media stream (S1) comprising the main content and the mapped alternative content. A method, computer program, computer program products and system are also disclosed.
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2.发明申请公开(公告)号：US20220209780A1
公开(公告)日：2022-06-30
申请号：US17599637
申请日：2019-04-05
发明人： Sunny Sharma , Lars Sundström , Bengt Erik Jonsson
摘要： A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.
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3.发明授权公开(公告)号：US11711089B2
公开(公告)日：2023-07-25
申请号：US17599637
申请日：2019-04-05
发明人： Sunny Sharma , Lars Sundström , Bengt Erik Jonsson
CPC分类号： H03M1/0675 , H03M1/08
摘要： A Successive Approximation Register, SAR, Analog to Digital Converter, ADC, (50) achieves high speed and accuracy by (1) alternating at least some decisions between sets of comparators having different accuracy and noise characteristics, and (2) unevenly allocating redundancy (in the form of LSBs of range) for successive decisions according to the accuracy/noise of the comparator used for the preceding decision. The redundancy allocation is compensated by the addition of decision cycles. Alternating between different comparators removes the comparator reset time (treset) from the critical path, at least for those decision cycles. The uneven allocation of redundancy—specifically, allocating more redundancy to decision cycles immediately following the use of a lower accuracy/higher noise comparators—compensates for the lower accuracy and prevents the need for larger redundancy (relative to the full-scale range of a decision cycle) later in the ADC process.
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公开(公告)号：US10897263B1
公开(公告)日：2021-01-19
申请号：US16874127
申请日：2020-05-14
摘要： A multipath bootstrapped sampling circuit includes a sampling capacitor, a sampling transistor interposed between the sampling capacitor and the analog input signal voltage, two bootstrap capacitors, and a bootstrap switching network periodically transitioning between a holding phase and a tracking phase. The bootstrap switching network includes a primary bootstrap path that drives only one load: the gate terminal of the sampling transistor. One or more auxiliary bootstrap paths drive other transistors in the bootstrap switching network. This absolutely minimizes the parasitic capacitance due to fan-out on the primary bootstrap path. Additionally, the provision of two (or more) bootstrap capacitors allows bulk terminals of transistors on the primary bootstrap path to be connected to an auxiliary bootstrap path, further reducing parasitic capacitance on the primary bootstrap path. Additional auxiliary bootstrap paths may be added, providing the opportunity to optimize each clock driver to a specific driven transistor. Additional bootstrap capacitors may be added, to distribute the capacitance among auxiliary bootstrap paths. The reduction in parasitic capacitance at the sampling transistor enhances its linearity, and hence accuracy, at very high frequencies.
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