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公开(公告)号：US10276229B2
公开(公告)日：2019-04-30
申请号：US15683906
申请日：2017-08-23
申请人： Teradyne, Inc.
摘要： Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edge of a version of a signal to provide a predefined logic level at the latch output; a first delay circuit that is controllable to configure a first delay, the first delay circuit being electrically connected to the first latch input and being for adjusting a rise portion of a skew in a first version of the signal; and a second delay circuit that is controllable to configure a second delay, the second delay circuit being electrically connected to the second latch input and being for adjusting a fall portion of the skew in a second version the signal.
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公开(公告)号：US20190069394A1
公开(公告)日：2019-02-28
申请号：US15683901
申请日：2017-08-23
申请人： Teradyne, Inc.
摘要： An example method performed for a circuit path includes: receiving signals in the circuit path; and controlling states of the signals in the circuit path based on skews produced by circuits electrically connected in series in the circuit path. The states are controlled by inverting or not inverting the signals in the circuit path so that skews produced by different circuits in the circuit paths at least partially cancel.
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公开(公告)号：US12041713B2
公开(公告)日：2024-07-16
申请号：US15683901
申请日：2017-08-23
申请人： Teradyne, Inc.
IPC分类号： H05K1/02 , G06F1/10 , G06F30/30 , G06F30/3312 , G06F119/12 , H03K19/003
CPC分类号： H05K1/0248 , G06F1/10 , G06F30/30 , G06F30/3312 , H03K19/00323 , H05K1/0298 , G06F2119/12
摘要： An example method performed for a circuit path includes: receiving signals in the circuit path; and controlling states of the signals in the circuit path based on skews produced by circuits electrically connected in series in the circuit path. The states are controlled by inverting or not inverting the signals in the circuit path so that skews produced by different circuits in the circuit paths at least partially cancel.
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公开(公告)号：US09503065B1
公开(公告)日：2016-11-22
申请号：US14840498
申请日：2015-08-31
申请人： Teradyne, Inc.
CPC分类号： H03K5/14 , G06F1/10 , H03K3/012 , H03K3/0375 , H03K3/356
摘要： Example circuitry includes: a first sampling circuit configured to operate based on a first clock signal, to receive data, and to sample the data, where the first clock signal is calibrated to compensate for a first timing error in a rising edge of the data; a second sampling circuit configured to operate based on a second clock signal, to receive the data, and to sample the data, where the second first clock signal is calibrated to compensate for a second timing error in a falling edge of the data; and a third sampling circuit to receive the data and a third clock signal, to sample the data based on the third clock signal to produce sampled data, and to control an output of the circuitry based on the sampled data to be either an output of the first sampling circuit or an output of the second sampling circuit.
摘要翻译： 示例电路包括：第一采样电路，被配置为基于第一时钟信号进行操作，以接收数据并对数据采样，其中第一时钟信号被校准以补偿数据的上升沿中的第一定时误差; 第二采样电路，被配置为基于第二时钟信号进行操作，以接收所述数据，并对所述数据进行采样，其中所述第二第一时钟信号被校准以补偿所述数据的下降沿中的第二定时误差; 以及第三采样电路，用于接收数据和第三时钟信号，以基于第三时钟信号对数据进行采样以产生采样数据，并且基于采样数据将电路的输出控制为是 第一采样电路或第二采样电路的输出。
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公开(公告)号：US10996272B2
公开(公告)日：2021-05-04
申请号：US14470574
申请日：2014-08-27
申请人： Teradyne, Inc.
IPC分类号： H03K3/037 , G01R31/3183 , H03K5/04 , H03K3/033 , H03K5/00 , G01R31/319
摘要： An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.
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公开(公告)号：US20190066757A1
公开(公告)日：2019-02-28
申请号：US15683906
申请日：2017-08-23
申请人： Teradyne, Inc.
摘要： Example circuitry to adjust a rise-fall skew in a signal includes: a latch including a first latch input, a second latch input, and a latch output, each of the first latch input and the second latch input being responsive to a rising edge of a version of a signal to provide a predefined logic level at the latch output; a first delay circuit that is controllable to configure a first delay, the first delay circuit being electrically connected to the first latch input and being for adjusting a rise portion of a skew in a first version of the signal; and a second delay circuit that is controllable to configure a second delay, the second delay circuit being electrically connected to the second latch input and being for adjusting a fall portion of the skew in a second version the signal.
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公开(公告)号：US20160065183A1
公开(公告)日：2016-03-03
申请号：US14470574
申请日：2014-08-27
申请人： Teradyne, Inc.
IPC分类号： H03K3/037 , G01R31/3183 , H03K5/04
CPC分类号： G01R31/318392 , G01R31/31917 , H03K3/033 , H03K5/04 , H03K2005/00013
摘要： An example one-shot circuit includes: circuitry including a set-reset (SR) latch to produce an output pulse of controlled duration in response to an input signal rising edge, where the SR latch includes a first circuit input and a second circuit input; a circuit path to provide a signal to the first circuit input; and a delay element connected to the circuit path and to the second circuit input.
摘要翻译： 示例性单触发电路包括：包括设置复位（SR）锁存器的电路，其响应于输入信号上升沿产生受控持续时间的输出脉冲，其中SR锁存器包括第一电路输入和第二电路输入; 用于向第一电路输入提供信号的电路路径; 以及连接到电路路径和第二电路输入端的延迟元件。
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