公开(公告)号：US06335903B2

公开(公告)日：2002-01-01

申请号：US09778785

申请日：2001-02-08

申请人： Tetsuhito Nakamura ,  Naonobu Sukegawa ,  Tsuguo Matsuura ,  Masanao Ito

发明人： Tetsuhito Nakamura ,  Naonobu Sukegawa ,  Tsuguo Matsuura ,  Masanao Ito

IPC分类号： G11C800

CPC分类号： G06F13/1631 ,  G06F12/0215

摘要： A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.

摘要翻译： 具有DRAM或同步DRAM作为存储单元的存储器系统。 存储器控制器，其与从存储器访问请求生成器接收的存储器访问请求相对应地控制存储器单元，具有用于存储从发布的存储器访问请求中提取的行地址的行地址缓冲器，避免将相同行地址注册到不同的位置 用于存储指向存储行地址的行地址缓冲器中的注册条目的指针寄存器，对应检测电路，通过比较存储的指针来检测发出的访问请求的行地址是否相互对应;存储器单元控制 电路，其连续地向DRAM发送具有彼此对应的行地址的多个请求的列地址。

公开(公告)号：US5978894A

公开(公告)日：1999-11-02

申请号：US757997

申请日：1996-11-27

申请人： Naonobu Sukegawa ,  Masanao Ito ,  Yoshiko Tamaki

发明人： Naonobu Sukegawa ,  Masanao Ito ,  Yoshiko Tamaki

IPC分类号： G06F12/00

CPC分类号： G06F12/00 ,  Y10S707/99953 ,  Y10S707/99955

摘要： To realize interprocessor data transfer with the data receive area not fixed in the real memory and with less overhead for synchronization, the send node sends to the destination node, data, a virtual address of a receive area, an address of a receive control flag, a comparison value, and a comparison method. Network adaptor in the destination node judges whether the transfer condition is fulfilled, based on the comparison value, the comparison method and the semaphore in the receive control flag designated by the receive control flag address. Network adaptor further detects whether the receive area of the virtual address is in the main storage, based on the virtual address and the address translation table. The send data is stored in the receive buffer provided in the area for OS, when the above-mentioned condition is not fulfilled or the receive area is not in the main storage. Either when the destination node program issues a specific system call or when the program issues a reading instruction to the data in the receive area and a page fault is generated, OS moves the send data from the receive buffer to the receive area.

摘要翻译： 为了实现与实际存储器中不固定的数据接收区域的处理器间数据传输，并且具有较少的同步开销，发送节点向目的地节点发送数据，接收区域的虚拟地址，接收控制标志的地址， 比较值和比较方法。 目的地节点中的网络适配器根据由接收控制标志地址指定的接收控制标志中的比较值，比较方法和信号量来判断传送条件是否被满足。 网络适​​配器还基于虚拟地址和地址转换表来检测虚拟地址的接收区域是否在主存储器中。 当不满足上述条件或接收区域不在主存储器中时，发送数据被存储在用于OS的区域中的接收缓冲器中。 当目的地节点程序发出特定的系统调用时，或者当程序向接收区域中的数据发出读取指令并产生页面错误时，OS将发送数据从接收缓冲器移动到接收区域。

公开(公告)号：US5392443A

公开(公告)日：1995-02-21

申请号：US855056

申请日：1992-03-19

申请人： Tadayuki Sakakibara ,  Katsuyoshi Kitai ,  Yasuhiro Inagami ,  Yoshiko Tamaki ,  Teruo Tanaka ,  Tadaaki Isobe ,  Shigeko Yazawa ,  Masanao Ito

发明人： Tadayuki Sakakibara ,  Katsuyoshi Kitai ,  Yasuhiro Inagami ,  Yoshiko Tamaki ,  Teruo Tanaka ,  Tadaaki Isobe ,  Shigeko Yazawa ,  Masanao Ito

IPC分类号： G06F12/06 ,  G06F15/78 ,  G06F15/16

CPC分类号： G06F15/8076 ,  G06F12/0607

摘要： A plurality of storage control units are employed in the storage control unit section; moreover, two requester modules are adopted in association with these storage control units. Each memory module is constituted with as many access bank groups as there are storage control units. The access bank groups operate in concurrent fashion and are accessible from any one of the storage control units. In the element assignment, a plurality of request control units in each requester module and a plurality of vector data controllers in each vector register unit are respectively assigned with serial numbers beginning from zero. For a vector data controller, a number assigned thereto is divided by the request module count to attain a remainder such that the vector data controller is assigned to a request module having a number identical to the value of the remainder. Furthermore, a request queue is disposed at a stage preceding each priority unit and a request send-out unit is arranged to store therein a state of the request queue and to control a request transmission from each request control unit. Addresses are assigned to the respective memory modules, bank groups, and banks according to skew schemes respectively suitable therefor.

摘要翻译： 在存储控制单元部分中采用多个存储控制单元; 此外，与这些存储控制单元相关联地采用两个请求者模块。 每个存储器模块由与存储控制单元一样多的存取组组构成。 访问存储组以并行方式操作，并且可以从任何一个存储控制单元访问。 在元素分配中，每个请求者模块中的多个请求控制单元和每个向量寄存器单元中的多个向量数据控制器分别被分配从零开始的序列号。 对于矢量数据控制器，分配给它的数字被请求模块计数除以获得余数，使得矢量数据控制器被分配给具有与其余值相同数目的请求模块。 此外，请求队列设置在每个优先级单元之前的阶段，并且请求发送单元被布置为在其中存储请求队列的状态并且控制来自每个请求控制单元的请求传输。 根据分别适合的偏移方案将地址分配给相应的存储器模块，存储体组和存储体。

公开(公告)号：US20050166089A1

公开(公告)日：2005-07-28

申请号：US11017942

申请日：2004-12-22

申请人： Masanao Ito ,  Tadayuki Sakakibara

发明人： Masanao Ito ,  Tadayuki Sakakibara

IPC分类号： G06F15/177 ,  G06F9/46 ,  G06F11/00 ,  G06F11/22

CPC分类号： G06F11/079 ,  G06F11/0724 ,  G06F11/3466

摘要： In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.

摘要翻译： 在包括一个或多个处理器的信息处理系统中，以预定频率执行诊断程序以诊断处理器。 诊断程序以预定的频率，以预定的时间间隔生成一个或多个处理或线程，例如诊断处理器。 生成的进程或线程在每个处理器上执行诊断，并且在处理器中检测到故障的进程或线程通过将故障信息存储在存储器中来完成其执行。 除了故障处理器之外的另一个处理器的进程或线程是指有关故障处理器的故障信息，并执行故障排除过程。

公开(公告)号：US07421618B2

公开(公告)日：2008-09-02

申请号：US11017942

申请日：2004-12-22

申请人： Masanao Ito ,  Tadayuki Sakakibara

发明人： Masanao Ito ,  Tadayuki Sakakibara

IPC分类号： G06F11/00

CPC分类号： G06F11/079 ,  G06F11/0724 ,  G06F11/3466

摘要： In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.

摘要翻译： 在包括一个或多个处理器的信息处理系统中，以预定频率执行诊断程序以诊断处理器。 诊断程序以预定的频率，以预定的时间间隔生成一个或多个处理或线程，例如诊断处理器。 生成的进程或线程在每个处理器上执行诊断，并且在处理器中检测到故障的进程或线程通过将故障信息存储在存储器中来完成其执行。 除了故障处理器之外的另一个处理器的进程或线程是指有关故障处理器的故障信息，并执行故障排除过程。

公开(公告)号：US6044450A

公开(公告)日：2000-03-28

申请号：US824486

申请日：1997-03-27

申请人： Yuji Tsushima ,  Yoshikazu Tanaka ,  Yoshiko Tamaki ,  Masanao Ito ,  Kentaro Shimada ,  Yonetaro Totsuka ,  Shigeo Nagashima

发明人： Yuji Tsushima ,  Yoshikazu Tanaka ,  Yoshiko Tamaki ,  Masanao Ito ,  Kentaro Shimada ,  Yonetaro Totsuka ,  Shigeo Nagashima

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F7/00

CPC分类号： G06F9/30025 ,  G06F9/30178 ,  G06F9/3853

摘要： Each small instruction in a VLIW instruction (long instruction) is added with the number of NOP instructions which succeed the small instruction, and these NOP instructions are deleted from the succeeding long instruction. A plurality of long instructions are therefore time-compressed. Thereafter, a plurality of small instructions in each long instruction are divided into a plurality of groups, and a combination of operation codes (OP codes) of small instructions in each group is replaced by a group code to generate a compressed, grouped instruction. Each long instruction is therefore space-compressed. An instruction expanding unit has an instruction expanding circuit for each grouped instruction. Each instruction expanding circuit expands one grouped instruction in a long instruction, generates a group of small instructions represented by the grouped instruction, and supplies the group of generated small instructions to respective function units via a decode unit. In this case, each instruction expanding circuit supplies after each small instruction NOP instructions same in number as that designated by a NOP number associated with each small instruction in this grouped instruction.

摘要翻译： VLIW指令（长指令）中的每个小指令都加上小指令成功的NOP指令数，并从后续长指令中删除这些NOP指令。 因此，多个长指令被时间压缩。 此后，每个长指令中的多个小指令被分成多个组，并且组中的小指令的操作码（OP代码）的组合被组代码替换以生成压缩的分组指令。 因此，每个长指令都是空间压缩的。 指令扩展单元具有用于每个分组指令的指令扩展电路。 每个指令扩展电路在长指令中扩展一个分组指令，生成由分组指令表示的一组小指令，并且经由解码单元将所生成的小指令组提供给各个功能单元。 在这种情况下，每个指令扩展电路在与分组指令中的每个小指令相关联的NOP号指定的每个小指令NOP指令之后提供数量相同的每个指令扩展电路。