公开(公告)号：US20110235401A1

公开(公告)日：2011-09-29

申请号：US13052214

申请日：2011-03-21

申请人： Tetsuji KUNITAKE ,  Takashi Shigeoka ,  Takayuki Tsukamoto ,  Hironori Wakai ,  Hisashi Kato

发明人： Tetsuji KUNITAKE ,  Takashi Shigeoka ,  Takayuki Tsukamoto ,  Hironori Wakai ,  Hisashi Kato

IPC分类号： G11C11/00 ,  H05K13/00

CPC分类号： H01L27/24 ,  G11C8/08 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0083 ,  H01L27/1021

摘要： A nonvolatile semiconductor memory device according to an embodiment herein includes a memory cell array. The memory cell array includes memory cells each provided between a first line and a second line and each including a variable resistor. A control circuit applies through the first and second lines a voltage necessary for a forming operation of the memory cell. A current limiting circuit limits a value of a current flowing across the memory cell during the forming operation to a certain limit value. The control circuit repeats an operation of applying the voltage by setting the limit value to a certain value and an operation of changing the limit value from the certain value, until forming of the memory cell is achieved.

摘要翻译： 根据本文实施例的非易失性半导体存储器件包括存储单元阵列。 存储单元阵列包括各自设置在第一线路和第二线路之间并且各自包括可变电阻器的存储器单元。 控制电路通过第一和第二行施加存储单元的形成操作所需的电压。 电流限制电路将在成形操作期间流过存储器单元的电流的值限制到某一极限值。 控制电路重复通过将极限值设定为一定值来施加电压的操作和从该特定值改变极限值的操作，直到实现存储单元的形成。

公开(公告)号：US20120075913A1

公开(公告)日：2012-03-29

申请号：US13235431

申请日：2011-09-18

申请人： Tetsuji KUNITAKE ,  Kenichi Murooka

发明人： Tetsuji KUNITAKE ,  Kenichi Murooka

IPC分类号： G11C11/21

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C8/14 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2213/71

摘要： A nonvolatile semiconductor memory device includes: a memory cell array which has a plurality of first lines, a plurality of second lines intersecting the plurality of first lines and a plurality of memory cells which store an electrically rewritable resistance value as data in a non-volatile manner; a first decoder which is connected to one ends of the plurality of first lines and selects the first lines; a second decoder which is connected to the plurality of second lines and selects the second lines; and a voltage applying circuit which is connected to one of the first and second decoders and which applies a predetermined voltage between the first and second lines selected by the first and second decoders. The second decoder sequentially selects the second lines in a direction from the other ends to the one ends of the first lines.

摘要翻译： 非易失性半导体存储器件包括：存储单元阵列，其具有多个第一线，与多条第一线相交的多条第二线，以及存储电可重写电阻值作为非易失性数据的多个存储单元 方式; 第一解码器，其连接到所述多个第一线的一端并选择所述第一线; 第二解码器，连接到所述多个第二线并选择所述第二线; 以及电压施加电路，其连接到第一和第二解码器中的一个，并且在由第一和第二解码器选择的第一和第二线之间施加预定电压。 第二解码器从第一行的另一端到一端的方向依次选择第二行。