公开(公告)号：US08891277B2

公开(公告)日：2014-11-18

申请号：US13313186

申请日：2011-12-07

申请人： Kenichi Murooka

发明人： Kenichi Murooka

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： H01L27/2481 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/78 ,  H01L21/768 ,  H01L27/2454 ,  H01L29/66666 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

摘要翻译： 根据一个实施例，存储器件包括第一至第三互连，存储器单元和选择器。 第一至第三互连分别沿着第一至第三方向设置。 存储单元包括形成在第三互连件的第一方向上彼此面对的两个侧表面上的可变电阻层。 选择器将第三互连与第一互连耦合。 其中一个选择器包括一个半导体层，该半导体层设置在相互连接的第三互连中的一个和第一互连中的相关一个之间，以及形成在半导体层的在第一方向上彼此相对的两个侧表面上的栅极之间的栅极绝缘膜。

公开(公告)号：US08498142B2

公开(公告)日：2013-07-30

申请号：US13072029

申请日：2011-03-25

申请人： Kenichi Murooka

发明人： Kenichi Murooka

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0033 ,  G11C2013/0092 ,  G11C2213/71 ,  G11C2213/72

摘要： A memory includes memory cells each includes a resistance change element and a diode, and each memory cell between one of row lines and one of column lines, a first decoder which selects one of the row lines as a selected row line, a second decoder which selects one of the column lines as a selected column line, a voltage pulse generating circuit which generates a voltage pulse, a voltage pulse shaping circuit which makes a rise time and a fall time of the voltage pulse longer, and a control circuit which applies the voltage pulse outputting from the voltage pulse shaping circuit to unselected column lines except the selected column line, and which applies a fixed potential to unselected row lines except the selected row line, in a data writing to a memory cell which is provided between the selected row line and the selected column line.

摘要翻译： 存储器包括各自包括电阻变化元件和二极管的存储单元，以及行线和列线之一之间的每个存储单元，选择行行之一作为所选行行的第一解码器，第二解码器， 选择列线之一作为选择的列线，产生电压脉冲的电压脉冲发生电路，使电压脉冲的上升时间和下降时间更长的电压脉冲整形电路以及施加电压脉冲的控制电路 电压脉冲从电压脉冲整形电路输出到除了所选列线之外的未选择的列线，并且在设置在所选择的行之间的存储单元的数据写入中将固定电位施加到除所选行行之外的未选行行 行和所选列行。

公开(公告)号：US20130148400A1

公开(公告)日：2013-06-13

申请号：US13313186

申请日：2011-12-07

申请人： Kenichi MUROOKA

发明人： Kenichi MUROOKA

IPC分类号： G11C5/06

CPC分类号： H01L27/2481 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1006 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/78 ,  H01L21/768 ,  H01L27/2454 ,  H01L29/66666 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149 ,  H01L45/1608

摘要： According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

摘要翻译： 根据一个实施例，存储器件包括第一至第三互连，存储器单元和选择器。 第一至第三互连分别沿着第一至第三方向设置。 存储单元包括形成在第三互连件的第一方向上彼此面对的两个侧表面上的可变电阻层。 选择器将第三互连与第一互连耦合。 其中一个选择器包括一个半导体层，该半导体层设置在相互连接的第三互连中的一个和第一互连中的相关一个之间，以及形成在半导体层的在第一方向上彼此相对的两个侧表面上的栅极之间的栅极绝缘膜。

公开(公告)号：US08391048B2

公开(公告)日：2013-03-05

申请号：US12846198

申请日：2010-07-29

申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Kenichi Murooka ,  Hirofumi Inoue ,  Hiroshi Kanno

IPC分类号： G11C11/00

CPC分类号： G11C13/0061 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092

摘要： A non-volatile semiconductor memory device according to an aspect of embodiments of the present invention includes a memory cell array including: multiple first wirings; multiple second wirings crossing the multiple first wirings; and multiple electrically rewritable memory cells respectively arranged at intersections of the first wirings and the second wirings, and each formed of a variable resistor which stores a resistance value as data in a non-volatile manner. The non-volatile semiconductor memory device according to an aspect of the embodiments of the present invention further includes a controller for selecting a given one of the memory cells, generating an erase pulse which is used for erasing data, and supplying the erase pulse to the selected memory cell. The erase pulse has a pulse width which is increased or decreased exponentially in accordance with an access path length to the selected memory cell.

摘要翻译： 根据本发明的实施例的非易失性半导体存储器件包括：存储单元阵列，包括：多个第一布线; 多个第二布线穿过多个第一布线; 以及分别布置在第一布线和第二布线的交点处的多个电可重写存储器单元，并且每个由可变电阻器形成，其以非易失性方式存储电阻值作为数据。 根据本发明的实施例的一个方面的非易失性半导体存储器件还包括一个控制器，用于选择给定的一个存储单元，产生用于擦除数据的擦除脉冲，并将擦除脉冲提供给 选择的存储单元。 擦除脉冲具有根据到所选存储单元的访问路径长度指数地增加或减少的脉冲宽度。

公开(公告)号：US08320157B2

公开(公告)日：2012-11-27

申请号：US12876637

申请日：2010-09-07

申请人： Reika Ichihara ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Kenichi Murooka

发明人： Reika Ichihara ,  Takayuki Tsukamoto ,  Hiroshi Kanno ,  Kenichi Murooka

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/13 ,  G11C2213/34 ,  G11C2213/72

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of first wirings, a plurality of second wirings intersecting the plurality of first wirings, and a plurality of memory cells provided at the intersections of the plurality of first and second wirings and each including a non-ohmic element and a variable resistance element connected in series. The control circuit selects one of the plurality of memory cells, generates an erasing pulse for erasing data from the selected memory cell, and supplies the erasing pulse to the selected memory cell. The control circuit executes data erase by applying a voltage of the erasing pulse to the non-ohmic element in the reverse bias direction.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列和控制电路。 存储单元阵列包括多个第一布线，与多条第一布线相交的多条第二布线，以及多个存储单元，设置在多个第一布线和第二布线的交点处，每个包括非欧姆元件和 串联连接的可变电阻元件。 控制电路选择多个存储单元中的一个，产生用于从所选存储单元擦除数据的擦除脉冲，并将擦除脉冲提供给所选存储单元。 控制电路通过在反向偏置方向上向非欧姆元件施加擦除脉冲的电压来执行数据擦除。

公开(公告)号：US08222626B2

公开(公告)日：2012-07-17

申请号：US12705010

申请日：2010-02-12

申请人： Mitsuru Sato ,  Masanori Komura ,  Hiroshi Kanno ,  Kenichi Murooka

发明人： Mitsuru Sato ,  Masanori Komura ,  Hiroshi Kanno ,  Kenichi Murooka

IPC分类号： H01L45/00

CPC分类号： H01L27/1021 ,  G11C29/832 ,  G11C29/88 ,  G11C2213/72 ,  H01L27/24 ,  H01L29/0657 ,  H01L29/868

摘要： A semiconductor memory device includes first and second memory cells each including a variable resistance element and a diode and having a pillar shape, and an insulating layer provided between the first memory cell and the second memory cell and including a void. A central portion of the diode has a smaller width than widths of upper and lower portions of the diode.

摘要翻译： 一种半导体存储器件，包括：第一和第二存储单元，每个存储单元包括可变电阻元件和二极管，并具有柱形;以及绝缘层，设置在第一存储单元和第二存储单元之间并且包括空隙。 二极管的中心部分的宽度比二极管的上部和下部的宽度小。

公开(公告)号：US08084830B2

公开(公告)日：2011-12-27

申请号：US12556005

申请日：2009-09-09

申请人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

发明人： Hiroshi Kanno ,  Kenichi Murooka ,  Jun Hirota ,  Hideyuki Tabata

IPC分类号： H01L27/11

CPC分类号： H01L27/101 ,  H01L27/1021 ,  H01L27/1027

摘要： The memory cell is located at respective intersections between the first wirings and the second wirings. Each of the memory cells has a rectifier element and a variable resistance element connected in series. The rectifier element includes a p type first semiconductor region, and a n type second semiconductor region. The first semiconductor region is formed of, at least in part, silicon-germanium mixture (Si1-xGex (0

摘要翻译： 存储单元位于第一布线和第二布线之间的相应交点处。 每个存储单元具有串联连接的整流元件和可变电阻元件。 整流元件包括p型第一半导体区域和n型第二半导体区域。 第一半导体区域至少部分地由硅 - 锗混合物（Si1-xGex（0

公开(公告)号：US20110122676A1

公开(公告)日：2011-05-26

申请号：US12887043

申请日：2010-09-21

申请人： Kenichi MUROOKA ,  Hirofumi Inoue

发明人： Kenichi MUROOKA ,  Hirofumi Inoue

IPC分类号： G11C11/00

CPC分类号： G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/35 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/149

摘要： According to one embodiment, a semiconductor memory device includes: word lines; bit lines; an insulating film; an interlayer insulating film; and a resistance varying material. The word lines, the bit lines and the insulating film configure a field-effect transistor at each of the intersections of the word lines and the bit lines. The field-effect transistor has one of the word lines as a control electrode and one of the bit lines as a channel region. The field-effect transistor and the resistance varying material configure a memory cell having the field-effect transistor and the resistance varying material connected in parallel. Each of the bit lines includes a first surface opposing the word lines, and a second surface on an opposite side to the first surface. The resistance varying material is disposed in contact with the second surface and has a portion thereof in contact with the interlayer insulating film.

摘要翻译： 根据一个实施例，半导体存储器件包括：字线; 位线 绝缘膜; 层间绝缘膜; 和电阻变化材料。 字线，位线和绝缘膜在字线和位线的每个交点处构成场效应晶体管。 场效应晶体管具有作为控制电极的字线之一和位线之一作为沟道区。 场效应晶体管和电阻变化材料配置具有并联连接的场效应晶体管和电阻变化材料的存储单元。 每个位线包括与字线相对的第一表面和与第一表面相反的一侧上的第二表面。 电阻变化材料设置成与第二表面接触并且其一部分与层间绝缘膜接触。

公开(公告)号：US09673389B2

公开(公告)日：2017-06-06

申请号：US13357149

申请日：2012-01-24

申请人： Kenichi Murooka

发明人： Kenichi Murooka

IPC分类号： H01L27/24 ,  H01L45/00

CPC分类号： H01L27/249 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/2436 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/16

摘要： According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.

公开(公告)号：US08766225B2

公开(公告)日：2014-07-01

申请号：US13040764

申请日：2011-03-04

申请人： Kenichi Murooka ,  Hiroshi Kanno

发明人： Kenichi Murooka ,  Hiroshi Kanno

IPC分类号： H01L29/02

CPC分类号： H01L27/1021 ,  H01L27/101

摘要： According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.

摘要翻译： 根据实施例，存储装置包括彼此平行布置的行线，彼此平行布置以与行线相交的列线，以及设置在行线和列线的每个交叉处的存储单元，并且包括 与电阻变化元件串联连接的电阻变化元件和二极管。 二极管包括一个包含第一导电类型的杂质的第一半导体区的堆叠，含有比第一半导体区低的浓度的第一导电类型的杂质的第二半导体区和含有杂质的第三半导体区 第二导电类型。 与第一半导体区域相邻的第一相邻部分中的二极管的第二半导体区域中的杂质浓度高于与第三半导体区域相邻的第二相邻部分中的杂质浓度。