公开(公告)号：US08633491B2

公开(公告)日：2014-01-21

申请号：US12805851

申请日：2010-08-20

申请人： Tetsuya Kawamura ,  Masashi Sato ,  Yoshiki Watanabe ,  Hiroaki Iwato ,  Masafumi Hirata

发明人： Tetsuya Kawamura ,  Masashi Sato ,  Yoshiki Watanabe ,  Hiroaki Iwato ,  Masafumi Hirata

IPC分类号： H01L29/786 ,  H01L21/8232

CPC分类号： H01L27/1288 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1214 ,  H01L29/41733

摘要： An etching resist including first and second portions, the first portion being thicker than the second portion, is formed on a metallic layer. Through the etching resist, a semiconductor layer and the metallic layer are patterned by etching so as to form a wiring from the metallic layer and leave the semiconductor layer under the wiring. An electrical test is conducted on the wiring. The second portion is removed while the first portion is left unremoved. Selective etching is performed through the first portion so as to leave the semiconductor layer unetched to pattern the wiring to be divided into drain and source electrodes. A substrate is cut. In patterning the wiring, the wiring is etched to be cut at a position closer to a cutting line of the substrate with respect to the drain and source electrodes, while leaving the semiconductor layer unetched.

摘要翻译： 包括第一部分和第二部分的蚀刻抗蚀剂，第一部分比第二部分厚，形成在金属层上。 通过蚀刻抗蚀剂，通过蚀刻对半导体层和金属层进行图案化，以从金属层形成布线，并将半导体层留在布线下。 在接线上进行电气测试。 第二部分被移除，而第一部分不被删除。 通过第一部分进行选择性蚀刻，以使半导体层未蚀刻，以将布线图案化以划分为漏极和源极。 切割基材。 在对布线进行构图时，在不影响半导体层的情况下，相对于漏极和源极电极，在更靠近基板的切割线的位置蚀刻布线。

公开(公告)号：US20110042675A1

公开(公告)日：2011-02-24

申请号：US12805851

申请日：2010-08-20

申请人： Tetsuya Kawamura ,  Masashi Sato ,  Yoshiki Watanabe ,  Hiroaki Iwato ,  Masafumi Hirata

发明人： Tetsuya Kawamura ,  Masashi Sato ,  Yoshiki Watanabe ,  Hiroaki Iwato ,  Masafumi Hirata

IPC分类号： H01L29/22 ,  H01L21/66

CPC分类号： H01L27/1288 ,  H01L22/14 ,  H01L22/20 ,  H01L27/1214 ,  H01L29/41733

摘要： An etching resist including first and second portions, the first portion being thicker than the second portion, is formed on a metallic layer. Through the etching resist, a semiconductor layer and the metallic layer are patterned by etching so as to form a wiring from the metallic layer and leave the semiconductor layer under the wiring. An electrical test is conducted on the wiring. The second portion is removed while the first portion is left unremoved. Selective etching is performed through the first portion so as to leave the semiconductor layer unetched to pattern the wiring to be divided into drain and source electrodes. A substrate is cut. In patterning the wiring, the wiring is etched to be cut at a position closer to a cutting line of the substrate with respect to the drain and source electrodes, while leaving the semiconductor layer unetched.

摘要翻译： 包括第一部分和第二部分的蚀刻抗蚀剂，第一部分比第二部分厚，形成在金属层上。 通过蚀刻抗蚀剂，通过蚀刻对半导体层和金属层进行图案化，以从金属层形成布线，并将半导体层留在布线下。 在接线上进行电气测试。 第二部分被移除，而第一部分不被删除。 通过第一部分进行选择性蚀刻，以使半导体层未蚀刻，以将布线图案化以划分为漏极和源极。 切割基材。 在对布线进行构图时，在不影响半导体层的情况下，相对于漏极和源极电极，在更靠近基板的切割线的位置蚀刻布线。

公开(公告)号：US08289464B2

公开(公告)日：2012-10-16

申请号：US12773559

申请日：2010-05-04

申请人： Tetsuya Kawamura ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

发明人： Tetsuya Kawamura ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

IPC分类号： G02F1/1333 ,  G02F1/13

CPC分类号： G02F1/13624 ,  G02F1/136259 ,  G02F2001/136268

摘要： A liquid crystal display device includes pixels, each of which includes a first transistor and a second transistor. The size of the first transistor is larger than the size of the second transistor. In addition, channel widths and gate widths for the first transistor are larger than those of the second transistor. Also, the first transistor is located to be closer to a drain signal line provided for the pixel than the second transistor. In normal operation, the first transistor is coupled to the drain signal line and the second transistor is floating. However, if an abnormality occurs in the first transistor, it is cut off from the drain signal line and the second transistor is connected to the drain signal line by a repair line.

摘要翻译： 液晶显示装置包括像素，每个像素包括第一晶体管和第二晶体管。 第一晶体管的尺寸大于第二晶体管的尺寸。 此外，第一晶体管的沟道宽度和栅极宽度大于第二晶体管的沟道宽度和栅极宽度。 此外，第一晶体管位于比第二晶体管更靠近为像素提供的漏极信号线。 在正常操作中，第一晶体管耦合到漏极信号线，第二晶体管是浮置的。 然而，如果第一晶体管发生异常，则从漏极信号线断开，第二晶体管通过修复线连接到漏极信号线。

公开(公告)号：US20100214205A1

公开(公告)日：2010-08-26

申请号：US12773559

申请日：2010-05-04

申请人： Tetsuya KAWAMURA ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

发明人： Tetsuya KAWAMURA ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

IPC分类号： G09G3/36

CPC分类号： G02F1/13624 ,  G02F1/136259 ,  G02F2001/136268

摘要： A liquid crystal display device includes pixels, each of which includes a first transistor and a second transistor. The size of the first transistor is larger than the size of the second transistor. In addition, channel widths and gate widths for the first transistor are larger than those of the second transistor. Also, the first transistor is located to be closer to a drain signal line provided for the pixel than the second transistor. In normal operation, the first transistor is coupled to the drain signal line and the second transistor is floating. However, if an abnormality occurs in the first transistor, it is cut off from the drain signal line and the second transistor is connected to the drain signal line by a repair line.

摘要翻译： 液晶显示装置包括像素，每个像素包括第一晶体管和第二晶体管。 第一晶体管的尺寸大于第二晶体管的尺寸。 此外，第一晶体管的沟道宽度和栅极宽度大于第二晶体管的沟道宽度和栅极宽度。 此外，第一晶体管位于比第二晶体管更靠近为像素提供的漏极信号线。 在正常操作中，第一晶体管耦合到漏极信号线，第二晶体管是浮置的。 然而，如果第一晶体管发生异常，则从漏极信号线断开，第二晶体管通过修复线连接到漏极信号线。

公开(公告)号：US07764330B2

公开(公告)日：2010-07-27

申请号：US11737776

申请日：2007-04-20

申请人： Tetsuya Kawamura ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

发明人： Tetsuya Kawamura ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

IPC分类号： G02F1/136 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/13

CPC分类号： G02F1/13624 ,  G02F1/136259 ,  G02F2001/136268

摘要： A normal transistor CTFT connected to a data signal line DL and a pixel electrode PX and a spare transistor FTFT in a floating state are formed on a gate line GL. When an operational abnormality occurs in the normal transistor CTFT, the normal transistor CTFT is cut off from the data signal line DL and is cut off from the pixel electrode PX connected via a through hole TH by cutting lines CL. Thereafter, the spare transistor FTFT is connected to the data signal line DL and the pixel electrode PX by repair lines RL.

摘要翻译： 在栅极线GL上形成连接到数据信号线DL和像素电极PX以及浮置状态的备用晶体管FTFT的正常晶体管CTFT。 当在正常晶体管CTFT中发生操作异常时，从数据信号线DL切断正常晶体管CTFT，并且通过切割线CL从经由通孔TH连接的像素电极PX切断。 此后，备用晶体管FTFT通过修理线RL连接到数据信号线DL和像素电极PX。

公开(公告)号：US20080036936A1

公开(公告)日：2008-02-14

申请号：US11737776

申请日：2007-04-20

申请人： Tetsuya Kawamura ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

发明人： Tetsuya Kawamura ,  Masashi Sato ,  Masanori Ookawa ,  Kenta Kamoshida ,  Nagatoshi Kurahashi ,  Hiroaki Iwato

IPC分类号： G02F1/1333

CPC分类号： G02F1/13624 ,  G02F1/136259 ,  G02F2001/136268

摘要： A normal transistor CTFT connected to a data signal line DL and a pixel electrode PX and a spare transistor FTFT in a floating state are formed on a gate line GL. When an operational abnormality occurs in the normal transistor CTFT, the normal transistor CTFT is cut off from the data signal line DL and is cut off from the pixel electrode PX connected via a through hole TH by cutting lines CL. Thereafter, the spare transistor FTFT is connected to the data signal line DL and the pixel electrode PX by repair lines RL.

摘要翻译： 在栅极线GL上形成连接到数据信号线DL和像素电极PX以及浮置状态的备用晶体管FTFT的正常晶体管CTFT。 当在正常晶体管CTFT中发生操作异常时，从数据信号线DL切断正常晶体管CTFT，并且通过切割线CL从经由通孔TH连接的像素电极PX切断。 此后，备用晶体管FTFT通过修理线RL连接到数据信号线DL和像素电极PX。

公开(公告)号：US20080024691A1

公开(公告)日：2008-01-31

申请号：US11730867

申请日：2007-04-04

申请人： Noriyuki Okabe ,  Tetsuya Kawamura ,  Masashi Sato ,  Kenta Kamoshida

发明人： Noriyuki Okabe ,  Tetsuya Kawamura ,  Masashi Sato ,  Kenta Kamoshida

IPC分类号： G02F1/1333

CPC分类号： G02F1/13624 ,  G02F1/136259 ,  G02F2001/136268

摘要： A normal transistor CTFT connected to a data signal line DL and a pixel electrode PX and a spare transistor FTFT in a floating state are formed on a gate line GL. When an operational abnormality occurs in the normal transistor CTFT, the normal transistor CTFT is cut off from the data signal line DL and the pixel electrode PX by cutting lines CL. The spare transistor FTFT is connected to the data signal line DL and the pixel electrode PX by repair lines RL.

摘要翻译： 在栅极线GL上形成连接到数据信号线DL和像素电极PX以及浮置状态的备用晶体管FTFT的正常晶体管CTFT。 当在正常晶体管CTFT中发生操作异常时，通过切割线CL从数据信号线DL和像素电极PX切断正常晶体管CTFT。 备用晶体管FTFT通过修理线RL连接到数据信号线DL和像素电极PX。

公开(公告)号：US09472039B2

公开(公告)日：2016-10-18

申请号：US13419922

申请日：2012-03-14

申请人： Masashi Sato

发明人： Masashi Sato

IPC分类号： G06F7/00 ,  G07D11/00

CPC分类号： G07D11/0084 ,  G07D11/0051

摘要： According to one embodiment, paper sheet handling apparatus includes inspecting module configured to detect denominations and directions of paper sheets, accumulating modules configured to accumulate paper sheets, storing module configured to store setting information in which accumulating modules are associated with denominations and directions of paper sheets, sorting module configured to specify accumulating module which accumulates paper sheets based on denomination and direction and setting information and to convey paper sheets to specified accumulating module, controlling module configured to display setting screen by displaying module based on setting information and to update setting information based on operation input to operating module.

摘要翻译： 根据一个实施例，纸张处理装置包括检查模块，其被配置为检测纸张的面额和方向，累积被配置为累积纸张的模块，存储模块，其被配置为存储累积模块与纸张的面额和方向相关联的设置信息 分配模块，其被配置为指定基于面额和方向和设置信息累积纸张的累积模块，并将纸张传送到指定的累积模块，控制模块被配置为基于设置信息显示模块来显示设置屏幕，并且基于设置信息更新设置信息 操作输入到操作模块。

公开(公告)号：US09111666B2

公开(公告)日：2015-08-18

申请号：US13885542

申请日：2011-12-26

申请人： Toyoki Furukawa ,  Masashi Sato

发明人： Toyoki Furukawa ,  Masashi Sato

IPC分类号： H01B7/00 ,  H01B3/30 ,  H01B3/42 ,  H01B7/17 ,  H01B7/282 ,  H01B7/28

CPC分类号： H01B7/17 ,  H01B3/301 ,  H01B3/423 ,  H01B7/2806 ,  H01B7/282

摘要： There are provided an automotive insulated wire, and automotive wiring harness that have an excellent resistance to a liquid, and an excellent resistance to an electrolyte, and that can be provided at low cost without causing an increase in cost. An automotive insulated wire (1) includes a metallic conductor (2) and an insulation covering layer (3) that covers the outer periphery of the metallic conductor, wherein the insulation covering layer is made from a mixed resin composition that contains resin ingredients that contain an ingredient A: a polysulfone resin, and an ingredient B: an aromatic polyester resin, and wherein a total of 100 parts by mass of the ingredients A and B contained in the mixed resin composition consists of 95 to 60 parts by mass of the ingredient A, and 5 to 40 parts by mass of the ingredient B.

摘要翻译： 提供了具有优异的耐液体性和优异的电解质性的汽车绝缘线和汽车线束，并且可以以低成本提供，而不会导致成本增加。 汽车绝缘电线（1）包括金属导体（2）和覆盖金属导体的外周的绝缘覆盖层（3），其中绝缘覆盖层由含有树脂成分的混合树脂组合物制成，所述树脂成分含有 成分A：聚砜树脂和成分B：芳香族聚酯树脂，其中混合树脂组合物中所含的成分A和B的总计100质量份由95〜60质量份的成分 A和5〜40质量份的成分B.

公开(公告)号：US08558627B2

公开(公告)日：2013-10-15

申请号：US13337555

申请日：2011-12-27

申请人： Masashi Sato

发明人： Masashi Sato

IPC分类号： H03B1/00 ,  H03B5/32 ,  H01L41/053

CPC分类号： H03H9/1014

摘要： Provided is a surface mount crystal oscillator and a substrate sheet to prevent a decrease in a frequency variable amount by reducing electrostatic capacitance of the crystal oscillator. The surface mount crystal oscillator and the substrate sheet are each configured such that one end of a crystal holding terminal is connected to a corner terminal, and another end of the crystal holding terminal is formed from a center of a short side to be shorter than the one end so as to form an area in which no pattern is formed, and a pattern of a GND terminal is formed on that portion of a rear surface of a substrate which is opposed to the area in which no pattern is formed, so that the pattern (a crystal-mounted pattern) of the crystal holding terminal and the pattern of the GND terminal are not opposed to each other across the substrate.

摘要翻译： 提供了一种表面贴装晶体振荡器和基板，以通过降低晶体振荡器的静电电容来防止频率可变量的降低。 表面安装晶体振荡器和基板片均被构造成使得晶体保持端子的一端连接到角端子，并且晶体保持端子的另一端由短边的中心形成为短于 一端形成没有形成图案的区域，并且在与未形成图案的区域相对的基板的背面的部分上形成GND端子的图案，使得 晶体保持端子的图案（晶体安装图案）和GND端子的图案在基板上彼此不相对。