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公开(公告)号：US06806860B2
公开(公告)日：2004-10-19
申请号：US09964465
申请日：2001-09-28
IPC分类号： G09G336
CPC分类号： G09G3/3696 , G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G2330/021 , G09G2360/16
摘要： There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.
摘要翻译： 公开了一种液晶驱动电路，其被配置为将数字灰度数据的模拟电压提供给多条信号线中的每条信号线，所述电路包括：参考电压产生电路，被配置为输出对应于每个所述数字 灰度数据; 多个缓冲放大器，被配置为单独地执行所述各个模拟参考电压的缓冲; 灰度模式电路，被配置为基于从外部提供的灰度模式信号来确定所述数字灰度数据的灰度数; 以及放大器使能电路，被配置为基于所述灰度级模式电路的输出信号将所述多个缓冲放大器中的每一个设置为使能状态或禁用状态。
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公开(公告)号：US20080117237A1
公开(公告)日：2008-05-22
申请号：US12016511
申请日：2008-01-18
CPC分类号： G09G3/3696 , G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G2330/021 , G09G2360/16
摘要： There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.
摘要翻译： 公开了一种液晶驱动电路，其被配置为将数字灰度数据的模拟电压提供给多条信号线中的每条信号线，所述电路包括：参考电压产生电路，被配置为输出对应于每个所述数字 灰度数据; 多个缓冲放大器，被配置为单独地执行所述各个模拟参考电压的缓冲; 灰度模式电路，被配置为基于从外部提供的灰度模式信号来确定所述数字灰度数据的灰度数; 以及放大器使能电路，被配置为基于所述灰度级模式电路的输出信号将所述多个缓冲放大器中的每一个设置为使能状态或禁用状态。
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公开(公告)号：US06411162B1
公开(公告)日：2002-06-25
申请号：US09813958
申请日：2001-03-22
IPC分类号： H03F345
摘要： In an amplifier device, a negative output voltage (−) of a differential amplifier stage corresponding to an input signal voltage (Vin) is supplied to the gate of Output transistor M25 for charging electrical charges to Capacitive load (80). A current corresponding to a positive output voltage (+) of the differential amplifier stage is supplied to Node (A) through which the gate of Output transistor M26 for discharging electrical charges from Capacitive load (80) is connected to Constant current source (4). This current becomes a value (Iy+&Dgr;I) according to the voltage (Vin). By changing the gate voltage of Output transistor M26, it enters ON, and the electrical charges are discharged as a current I3 from Capacitive load (80). The voltage (Vin) is converted to a current by Voltage-current converter (1), and Current-voltage converter (2) then converts this current to a voltage. It is thereby possible to increase the driving ability of Output transistor M26 and to perform a response operation at high speed with low power consumption only by changing the current corresponding to the positive output voltage (+) of the differential pair.
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公开(公告)号：US07358951B2
公开(公告)日：2008-04-15
申请号：US10895320
申请日：2004-07-21
IPC分类号： G09G3/36
CPC分类号： G09G3/3696 , G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G2330/021 , G09G2360/16
摘要： There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.
摘要翻译： 公开了一种液晶驱动电路，其被配置为将数字灰度数据的模拟电压提供给多条信号线中的每条信号线，所述电路包括：参考电压产生电路，被配置为输出对应于每个所述数字 灰度数据; 多个缓冲放大器，被配置为单独地执行所述各个模拟参考电压的缓冲; 灰度模式电路，被配置为基于从外部提供的灰度模式信号来确定所述数字灰度数据的灰度数; 以及放大器使能电路，被配置为基于所述灰度级模式电路的输出信号将所述多个缓冲放大器中的每一个设置为使能状态或禁用状态。
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公开(公告)号：US07676528B2
公开(公告)日：2010-03-09
申请号：US11231762
申请日：2005-09-22
IPC分类号： G09G5/00
CPC分类号： G06F3/1415 , G09G3/2096 , G09G3/3688 , G09G5/006 , G09G5/008 , G09G2310/027 , G09G2330/06 , G09G2340/16 , G09G2370/045 , G09G2370/047
摘要： An image data processing apparatus includes: a data dividing unit dividing arithmetic image data into arithmetic pixel data corresponding to a signal line of a display device; an adder adding first data and second data; and a data delaying unit delaying the added data, wherein the first data is the divided arithmetic pixel data from the data dividing unit, and the second data is the delayed added arithmetic pixel data from the data delaying unit.
摘要翻译： 图像数据处理装置包括：数据划分单元，将运算图像数据分割成与显示装置的信号线对应的算术像素数据; 加法器，其添加第一数据和第二数据; 以及数据延迟单元延迟所添加的数据，其中所述第一数据是来自所述数据分割单元的分割的运算像素数据，并且所述第二数据是来自所述数据延迟单元的延迟加法运算像素数据。
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公开(公告)号：US07027027B2
公开(公告)日：2006-04-11
申请号：US10226198
申请日：2002-08-23
IPC分类号： G09G3/36
CPC分类号： H03F3/211 , G09G3/3614 , G09G2310/027 , H03F1/0277 , H03F2203/45371 , H03F2203/7236 , H03K5/2481
摘要： A differential amplifying circuit according to the present invention, comprising: a first differential pair having first and second transistors of the same conduction type, which outputs differential output signals in accordance with differential input signals supplied to gate terminals of said first and second transistors from differential output terminals; a second differential pair having third and fourth transistors having the same conduction type as that of said first and second transistors with threshold voltages different from each other, which outputs differential output signals in accordance with said differential input signals supplied to gate terminals of said third and fourth transistors from said differential output terminals; a bias supply part which supplies bias current to said first and second differential parts; and a differential pair control part which controls whether or not to operate said second differential pair.
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公开(公告)号：US20060221099A1
公开(公告)日：2006-10-05
申请号：US11231762
申请日：2005-09-22
IPC分类号： G09G5/00
CPC分类号： G06F3/1415 , G09G3/2096 , G09G3/3688 , G09G5/006 , G09G5/008 , G09G2310/027 , G09G2330/06 , G09G2340/16 , G09G2370/045 , G09G2370/047
摘要： An image data processing apparatus includes: a data dividing unit dividing arithmetic image data into arithmetic pixel data corresponding to a signal line of a display device; an adder adding first data and second data; and a data delaying unit delaying the added data, wherein the first data is the divided arithmetic pixel data from the data dividing unit, and the second data is the delayed added arithmetic pixel data from the data delaying unit.
摘要翻译： 图像数据处理装置包括：数据划分单元，将运算图像数据分割成与显示装置的信号线对应的算术像素数据; 加法器，其添加第一数据和第二数据; 以及数据延迟单元延迟所添加的数据，其中所述第一数据是来自所述数据分割单元的分割的运算像素数据，并且所述第二数据是来自所述数据延迟单元的延迟加法运算像素数据。
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公开(公告)号：US08593111B2
公开(公告)日：2013-11-26
申请号：US12559072
申请日：2009-09-14
IPC分类号： H02J7/00
CPC分类号： H02J7/0021 , H01M10/42 , H02J7/0031
摘要： In an assembled battery system, parallel battery blocks are connected in series. Each of the battery blocks includes battery unit modules connected in parallel, and each of the modules includes a battery unit and a fuse connected in series. The battery block is provided with a common connection line connected to a fuse monitoring module, and MOS-FETs each having a gate, source and drain, wherein the fuse is connected between the gate and source, and the drain is connected to the connection line. The FET is turned on and a voltage is applied to the connection line through the FET from the battery unit, when the fuse is blown out. Thus, the fuse monitoring module can detects the blowout of the fuse, and a control module can turn off a control switch to stop charging/discharging of the assembled battery in accordance with the control signal from the fuse monitoring module.
摘要翻译： 在组合电池系统中，并联电池块串联连接。 每个电池块包括并联连接的电池单元模块，并且每个模块包括串联连接的电池单元和熔丝。 电池块设有连接到保险丝监视模块的公共连接线，以及各自具有栅极，源极和漏极的MOS-FET，其中，熔丝连接在栅极和源极之间，漏极连接到连接线 。 当保险丝熔断时，FET被接通并且通过FET从电池单元向连接线施加电压。 因此，熔丝监视模块可以检测熔丝的喷出，并且控制模块可以根据来自熔丝监视模块的控制信号关闭控制开关以停止组电池的充电/放电。
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公开(公告)号：US08350547B2
公开(公告)日：2013-01-08
申请号：US12878271
申请日：2010-09-09
申请人： Takeshi Ueno , Tetsuro Itakura
发明人： Takeshi Ueno , Tetsuro Itakura
IPC分类号： G05F1/00
CPC分类号： H02M3/1563
摘要： A DC to DC converter includes an input terminal, an output terminal, first and second switches, an inductor, a smoothing unit, a first impedance element, a first resistor element, an operational amplifier and a control unit. The first switch is connected to the input terminal. The second switch is connected to the first switch and a ground terminal. The inductor is connected to the first switch and the output terminal. The smoothing unit is connected to the inductor and the ground terminal. The first impedance element is connected to the smoothing unit. The first resistor element is connected in series with the first impedance element. The operational amplifier is connected to the first impedance element. Reference voltage is added to the operational amplifier. The control unit controls the first and second switches according to a control signal outputted from the operational amplifier.
摘要翻译： DC-DC转换器包括输入端子，输出端子，第一和第二开关，电感器，平滑单元，第一阻抗元件，第一电阻元件，运算放大器和控制单元。 第一个开关连接到输入端。 第二开关连接到第一开关和接地端子。 电感器连接到第一开关和输出端子。 平滑单元连接到电感器和接地端子。 第一阻抗元件连接到平滑单元。 第一电阻元件与第一阻抗元件串联连接。 运算放大器连接到第一阻抗元件。 参考电压加到运算放大器上。 控制单元根据从运算放大器输出的控制信号来控制第一和第二开关。
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公开(公告)号：US20120241599A1
公开(公告)日：2012-09-27
申请号：US13308646
申请日：2011-12-01
申请人： Hiroshi Uemura , Ippei Akita , Tetsuro Itakura , Hideto Furuyama
发明人： Hiroshi Uemura , Ippei Akita , Tetsuro Itakura , Hideto Furuyama
摘要： According to one embodiment, a circuit comprises a first resistor configured to have one end to which a first voltage is input and the other end which outputs a second voltage and a first amplifier configured to have an inverting input connected to the other end of the first resistor and a noninverting input to which a third voltage is input. The circuit further comprises a first capacitor configured to have one end to which an output of the first amplifier is input and the other end to which the other end of the first resistor is connected. An output of the first amplifier or an output of a second amplifier connected to the other end of the first resistor is a fourth voltage. In the circuit, the first resistor and a mirror capacitance composed of the first capacitor and the first amplifier constitute a low-pass filter.
摘要翻译： 根据一个实施例，电路包括第一电阻器，其被配置为具有输入第一电压的一端和输出第二电压的另一端和配置成具有连接到第一电压的另一端的反相输入的第一放大器 电阻器和输入第三电压的同相输入端。 电路还包括第一电容器，其被配置为具有输入第一放大器的输出的一端和第一电阻器的另一端连接到的另一端。 连接到第一电阻器的另一端的第一放大器的输出或第二放大器的输出是第四电压。 在该电路中，由第一电容器和第一放大器组成的第一电阻器和反射镜电容器构成低通滤波器。
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