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    LOOK-UP TABLE READ
    1.
    发明申请
    LOOK-UP TABLE READ 有权

    公开(公告)号：US20240403054A1

    公开(公告)日：2024-12-05

    申请号：US18805711

    申请日：2024-08-15

    Applicant: Texas Instruments Incorporated

    Inventor： Naveen Bhoria ,  Dheera Balasubramanian Samudrala ,  Duc Bui ,  Alan Davis

    IPC: G06F9/30 ,  G06F3/06 ,  G06F9/355 ,  G06F9/38 ,  G06F9/445 ,  G06F12/02 ,  G06F12/0811 ,  G06F16/31 ,  G06F16/41 ,  G06F16/901 ,  G11C11/409

    Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

    CONDITIONAL BRANCH INSTRUCTIONS
    2.
    发明申请
    CONDITIONAL BRANCH INSTRUCTIONS 有权

    公开(公告)号：US20250060965A1

    公开(公告)日：2025-02-20

    申请号：US18427411

    申请日：2024-01-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Alexander Tessarolo ,  Venkatesh Natarajan ,  Alan Davis

    IPC: G06F9/38 ,  G06F9/30

    Abstract: Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions and cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

    Look-up table read
    4.
    发明授权
    Look-up table read 有权

    公开(公告)号：US11455169B2

    公开(公告)日：2022-09-27

    申请号：US16570640

    申请日：2019-09-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naveen Bhoria ,  Dheera Balasubramanian Samudrala ,  Duc Bui ,  Alan Davis

    IPC: G06F9/30 ,  G06F12/02 ,  G11C11/409 ,  G06F16/31 ,  G06F16/901 ,  G06F16/41 ,  G06F9/445 ,  G06F9/38 ,  G06F12/0811 ,  G06F3/06 ,  G06F9/355

    Abstract: A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

    Reducing overhead in processor array searching
    6.
    发明授权
    Reducing overhead in processor array searching 有权

    公开(公告)号：US12032966B2

    公开(公告)日：2024-07-09

    申请号：US17958219

    申请日：2022-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Alan Davis ,  Venkatesh Natarajan ,  Alexander Tessarolo

    IPC: G06F9/38 ,  G06F7/02

    CPC classification number: G06F9/3869 ,  G06F7/02

    Abstract: A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

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