公开(公告)号：US12266597B2

公开(公告)日：2025-04-01

申请号：US17563403

申请日：2021-12-28

Applicant: Texas Instruments Incorporated

Inventor： Jaimal Mallory Williamson ,  Chun Ping Lo ,  Yutaka Suzuki

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: An electronic device includes a multilevel package substrate with first and second levels, the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer, and the first level including a second trace layer with a stair shaped second conductive trace feature, the second conductive trace feature having a first portion with a first thickness, and a second portion, having a second thickness greater than the first thickness.

公开(公告)号：US20230378146A1

公开(公告)日：2023-11-23

申请号：US18320102

申请日：2023-05-18

Applicant: Texas Instruments Incorporated

Inventor： John Carlo Molina ,  Julian Carlo Barbadillo ,  Chun Ping Lo ,  Sylvester Ankamah-Kusi ,  Rajen Murugan ,  Thomas Kronenberg ,  Jonathan Noquil ,  Guangxu Li ,  Blake Travis ,  Jason Colte

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L25/16 ,  H01L23/49822 ,  H01L28/40 ,  H01L23/3121 ,  H01L24/16 ,  H01L23/49562 ,  H01L21/4857 ,  H01L21/56 ,  H01L2224/16227

Abstract: An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.

公开(公告)号：US20230207435A1

公开(公告)日：2023-06-29

申请号：US17563403

申请日：2021-12-28

Applicant: Texas Instruments Incorporated

Inventor： Jaimal Mallory Williamson ,  Chun Ping Lo ,  Yutaka Suzuki

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/49816 ,  H01L21/4853 ,  H01L24/16

Abstract: An electronic device includes a multilevel package substrate with first and second levels, the second level including a first trace layer with a first conductive trace feature, a conductive first via that contacts the first conductive trace feature, and a first dielectric layer, and the first level including a second trace layer with a stair shaped second conductive trace feature, the second conductive trace feature having a first portion with a first thickness, and a second portion, having a second thickness greater than the first thickness.