公开(公告)号：US20240128228A1

公开(公告)日：2024-04-18

申请号：US17971730

申请日：2022-10-24

申请人： Texas Instruments Incorporated

发明人： Aniceto Rabilas, JR. ,  Ray Fredric De Asis ,  Jason Colte

IPC分类号： H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： H01L24/48 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/85 ,  H01L24/45 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48175 ,  H01L2224/4846 ,  H01L2224/48465 ,  H01L2224/85986

摘要： An electronic device includes a package structure, a conductive terminal exposed outside the package structure, a semiconductor die in the package structure, and a bond wire having contiguous first and second portions. The first portion has a first end and a second end, the first end connected to the semiconductor die by a first bond and the second end connected to the conductive terminal by a second bond. The second portion has a first end and a second end, the first end of the second portion connected to the second end of the first portion, and the second end of the second portion connected to the conductive terminal by a third bond.

公开(公告)号：US20240063107A1

公开(公告)日：2024-02-22

申请号：US17892202

申请日：2022-08-22

申请人： Texas Instruments Incorporated

发明人： Jason Colte ,  Jerry Cayabyab ,  Julian Carlo Barbadillo ,  John Carlo Molina ,  Richard Sumalinog ,  Raust Glenn Magcaling ,  Ruby Ann Camenforte

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/49838 ,  H01L23/49822 ,  H01L21/4857 ,  H01L24/16 ,  H01L24/81 ,  H01L24/13 ,  H01L21/561 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/81815

摘要： An electronic device includes a multilevel package substrate, a semiconductor die mounted to the multilevel package substrate, and a package structure that encloses the semiconductor die and a portion of the multilevel package substrate. The multilevel package substrate has a first level, a second level, a first metal stack, and a second metal stack. The first metal stack includes a first set of contiguous metal structures of the first and second levels, the second metal stack includes a second set of contiguous metal structures of the first and second levels, the first and second metal stacks are spaced apart from one another, a first metal trace of the first metal stack partially overlaps a second metal trace of the second metal stack, and the first and second metal traces are in different levels of the multilevel package substrate.

公开(公告)号：US20230378146A1

公开(公告)日：2023-11-23

申请号：US18320102

申请日：2023-05-18

申请人： Texas Instruments Incorporated

发明人： John Carlo Molina ,  Julian Carlo Barbadillo ,  Chun Ping Lo ,  Sylvester Ankamah-Kusi ,  Rajen Murugan ,  Thomas Kronenberg ,  Jonathan Noquil ,  Guangxu Li ,  Blake Travis ,  Jason Colte

IPC分类号： H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L25/16 ,  H01L23/49822 ,  H01L28/40 ,  H01L23/3121 ,  H01L24/16 ,  H01L23/49562 ,  H01L21/4857 ,  H01L21/56 ,  H01L2224/16227

摘要： An example microelectronic device package includes: a multilayer package substrate comprising routing conductors spaced by dielectric material, the multilayer package substrate having a device side surface and an opposing board side surface, and having a recessed portion extending from the device side surface and exposing routing conductors beneath the device side surface of the multilayer package substrate; a semiconductor die mounted to the device side surface of the multilayer package substrate and coupled to the routing conductors; a passive component mounted to the routing conductors exposed in the recessed portion of the multilayer package substrate; and mold compound covering the semiconductor die, the passive component, and a portion of the multilayer package substrate.