公开(公告)号：US20160233294A1

公开(公告)日：2016-08-11

申请号：US15098452

申请日：2016-04-14

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. BABCOCK ,  Alexei SADOVNIKOV

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L21/8228 ,  H01L27/082

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

公开(公告)号：US20170309703A1

公开(公告)日：2017-10-26

申请号：US15647493

申请日：2017-07-12

Applicant: Texas Instruments Incorporated

Inventor： Jeffrey A. BABCOCK ,  Alexei SADOVNIKOV

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L29/08 ,  H01L29/04 ,  H01L27/082 ,  H01L21/8228 ,  H01L21/762 ,  H01L21/308 ,  H01L21/306 ,  H01L29/16 ,  H01L29/732 ,  H01L21/266

CPC classification number: H01L29/063 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/8228 ,  H01L21/82285 ,  H01L27/082 ,  H01L27/0826 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/732

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.