公开(公告)号：US12105550B2

公开(公告)日：2024-10-01

申请号：US16995852

申请日：2020-08-18

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  Rajeev Suvarna ,  Nikunj Khare

IPC: G06F1/12 ,  G06F13/24

CPC classification number: G06F1/12 ,  G06F13/24

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

公开(公告)号：US20180182440A1

公开(公告)日：2018-06-28

申请号：US15389814

申请日：2016-12-23

Applicant: Texas Instruments Incorporated

Inventor： Nikunj Khare ,  Rajeev Suvarna ,  Gregory A. North ,  Maneesh Soni

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/222 ,  H03K21/00

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

公开(公告)号：US20130177026A1

公开(公告)日：2013-07-11

申请号：US13734699

申请日：2013-01-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Maneesh Soni ,  William C. Wallace

IPC: H04L29/10

CPC classification number: H04L29/10 ,  G06F11/1004 ,  G06F13/00 ,  G06F13/385 ,  H04L12/40032

Abstract: This invention is a low level programmable logic that can communicate with Media Independent Interface (MII) (Ethernet) interface in a highly configurable manner under the control of a CPU. This invention is highly configurable for various existing and new Ethernet based communication standards, programmable in an easy to learn assembly language, low power and high performance

Abstract translation: 本发明是一种低级可编程逻辑，可在CPU的控制下以高度可配置的方式与媒体独立接口（MII）（以太网）接口进行通信。 本发明高度可配置用于各种现有和新的基于以太网的通信标准，可以易于学习的汇编语言编程，低功耗和高性能

公开(公告)号：US20240411341A1

公开(公告)日：2024-12-12

申请号：US18804364

申请日：2024-08-14

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  Rajeev Suvarna ,  Nikunj Khare

IPC: G06F1/12 ,  G06F13/24

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

公开(公告)号：US20180217630A1

公开(公告)日：2018-08-02

申请号：US15420267

申请日：2017-01-31

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  Rajeev Suvarna ,  Nikunj Khare

IPC: G06F1/12

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

公开(公告)号：US20200379505A1

公开(公告)日：2020-12-03

申请号：US16995852

申请日：2020-08-18

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  Rajeev Suvarna ,  Nikunj Khare

IPC: G06F1/12 ,  G06F13/24

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

公开(公告)号：US20140105022A1

公开(公告)日：2014-04-17

申请号：US14105493

申请日：2013-12-13

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  Amritpal S. Mundra ,  Thomas H. McKinney ,  Jagdish Doma

IPC: H04L12/823 ,  G06F9/30 ,  H04W88/02

CPC classification number: H04L47/32 ,  G06F9/3001 ,  H04L63/0263 ,  H04L69/22 ,  H04W88/02 ,  Y10T29/49002

Abstract: A packet filter (2500) for incoming communications packets includes extractor circuitry (2510) operable to extract data from a packet, and packet processor circuitry (2520) operable to concurrently mask (3010) the packet data from the extractor circuitry (2510), perform an arithmetic/logic operation (3020) on the packet to supply a packet drop signal (DROP), and perform a conditional limit operation and a conditional jump operation (3030).

Abstract translation: 用于输入通信分组的分组过滤器（2500）包括可操作以从分组提取数据的提取器电路（2510）和可操作以同时从提取器电路（2510）屏蔽（3010）分组数据的分组处理器电路（2520），执行 在分组上提供算术/逻辑运算（3020）以提供分组丢弃信号（DROP），并执行条件限制操作和条件跳转操作（3030）。

公开(公告)号：US10014041B1

公开(公告)日：2018-07-03

申请号：US15389814

申请日：2016-12-23

Applicant: Texas Instruments Incorporated

Inventor： Nikunj Khare ,  Rajeev Suvarna ,  Gregory A. North ,  Maneesh Soni

IPC: G11C7/22 ,  G11C7/10

Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.

公开(公告)号：US08902922B2

公开(公告)日：2014-12-02

申请号：US13734699

申请日：2013-01-04

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  William C. Wallace

IPC: H04L12/66 ,  H04L29/10 ,  G06F13/00 ,  G06F13/38 ,  G06F11/10 ,  H04L12/40

CPC classification number: H04L29/10 ,  G06F11/1004 ,  G06F13/00 ,  G06F13/385 ,  H04L12/40032

Abstract: This invention is a low level programmable logic that can communicate with Media Independent Interface (MII) (Ethernet) interface in a highly configurable manner under the control of a CPU. This invention is highly configurable for various existing and new Ethernet based communication standards, programmable in an easy to learn assembly language, low power and high performance.

Abstract translation: 本发明是一种低级可编程逻辑，可在CPU的控制下以高度可配置的方式与媒体独立接口（MII）（以太网）接口进行通信。 本发明高度可配置用于各种现有和新的基于以太网的通信标准，可以易于学习的汇编语言编程，低功耗和高性能。

公开(公告)号：US10788853B2

公开(公告)日：2020-09-29

申请号：US15420267

申请日：2017-01-31

Applicant: Texas Instruments Incorporated

Inventor： Maneesh Soni ,  Rajeev Suvarna ,  Nikunj Khare

IPC: G06F1/12 ,  G06F13/24

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.