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公开(公告)号：US20200379505A1
公开(公告)日：2020-12-03
申请号：US16995852
申请日：2020-08-18
Applicant: Texas Instruments Incorporated
Inventor： Maneesh Soni , Rajeev Suvarna , Nikunj Khare
Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
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公开(公告)号：US10788853B2
公开(公告)日：2020-09-29
申请号：US15420267
申请日：2017-01-31
Applicant: Texas Instruments Incorporated
Inventor： Maneesh Soni , Rajeev Suvarna , Nikunj Khare
Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
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Patent Agency Ranking
公开(公告)号：US10014041B1
公开(公告)日：2018-07-03
申请号：US15389814
申请日：2016-12-23
Applicant: Texas Instruments Incorporated
Inventor： Nikunj Khare , Rajeev Suvarna , Gregory A. North , Maneesh Soni
Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.
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公开(公告)号：US12105550B2
公开(公告)日：2024-10-01
申请号：US16995852
申请日：2020-08-18
Applicant: Texas Instruments Incorporated
Inventor： Maneesh Soni , Rajeev Suvarna , Nikunj Khare
Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
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5.发明申请公开(公告)号：US20180182440A1
公开(公告)日：2018-06-28
申请号：US15389814
申请日：2016-12-23
Applicant: Texas Instruments Incorporated
Inventor： Nikunj Khare , Rajeev Suvarna , Gregory A. North , Maneesh Soni
Abstract: Disclosed examples include interface circuits to transfer data between a first register in a fast clock domain and a second register in a slow clock domain, including a resettable synchronizer to provide a synchronized start signal synchronized to a slow clock signal to initiate a write from the first register to the second register according to a write request signal, a pulse generator circuit to provide a write enable pulse signal according to the synchronized start signal, a write control circuit to selectively connect an output of the first register to an input of the second register to write data from the first register to the second register according to the write enable pulse signal, and a dual flip-flop to provide a reset signal synchronized to a fast clock signal according to the write request signal to clear any prior pending write request and begin a new write operation.
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公开(公告)号：US20240411341A1
公开(公告)日：2024-12-12
申请号：US18804364
申请日：2024-08-14
Applicant: Texas Instruments Incorporated
Inventor： Maneesh Soni , Rajeev Suvarna , Nikunj Khare
Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
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公开(公告)号：US20180217630A1
公开(公告)日：2018-08-02
申请号：US15420267
申请日：2017-01-31
Applicant: Texas Instruments Incorporated
Inventor： Maneesh Soni , Rajeev Suvarna , Nikunj Khare
IPC: G06F1/12
Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
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