公开(公告)号：US09520861B1

公开(公告)日：2016-12-13

申请号：US14971465

申请日：2015-12-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Michael A. Wu ,  Sudipto Chakraborty

IPC: H03K3/03

CPC classification number: H03K3/0315

Abstract: A system to generate an oscillator signal. The system includes a multi-stage oscillator, where each stage generates an output. The system also includes a first weighting circuit coupled to the multi-stage oscillator. The first weighting circuit taps the outputs of at least some of the stages and applies a first variable weighting factor to each output of the tapped stages to generate a first weighted output for each of the tapped stages. The system also includes a first summing circuit coupled to the first weighting circuit. The first summing circuit sums the first weighted outputs of the tapped stages to produce the oscillator signal.

Abstract translation: 用于产生振荡器信号的系统。 该系统包括多级振荡器，其中每个级产生输出。 该系统还包括耦合到多级振荡器的第一加权电路。 第一加权电路抽取至少一些级的输出，并且将第一可变加权因子应用于抽头级的每个输出，以产生每个抽头级的第一加权输出。 该系统还包括耦合到第一加权电路的第一求和电路。 第一求和电路将抽头级的第一加权输出相加以产生振荡器信号。

公开(公告)号：US20150381191A1

公开(公告)日：2015-12-31

申请号：US14318228

申请日：2014-06-27

Applicant: Texas Instruments Incorporated

Inventor： Michael A. Wu ,  Sudipto Chakraborty

IPC: H03L7/099 ,  H03L7/08

CPC classification number: H03L7/0802 ,  H03L7/0996 ,  H03L7/16

Abstract: A circuit includes a ring oscillator component and a phase selecting component. The ring oscillator component outputs a clock signal having a clock frequency, fCLK, and has a number n of delay components connected in series. The phase selecting component outputs a feedback clock signal, and has a switching component. The switching component can be in a first state and a second state, and can switch from the first state to the second state. The switching component outputs, in the first state, an output of a first delay component such that a signal output from the first delay component is the feedback clock signal having a first phase. The switching component outputs, in the second state, an output of a second delay component such that a signal output from the second delay component is the feedback clock signal having a second phase.

Abstract translation: 电路包括环形振荡器部件和相位选择部件。 环形振荡器组件输出具有时钟频率fCLK的时钟信号，并且具有串联连接的数量n个延迟分量。 相位选择分量输出反馈时钟信号，具有开关元件。 切换部件可以处于第一状态和第二状态，并且可以从第一状态切换到第二状态。 开关部件在第一状态下输出第一延迟部件的输出，使得从第一延迟部件输出的信号是具有第一相位的反馈时钟信号。 切换部件在第二状态下输出第二延迟分量的输出，使得从第二延迟分量输出的信号是具有第二相位的反馈时钟信号。

公开(公告)号：US20140154850A1

公开(公告)日：2014-06-05

申请号：US14172608

申请日：2014-02-04

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC: H01L29/66

CPC classification number: H01L29/66825 ,  H01L21/2652 ,  H01L23/5223 ,  H01L27/11517 ,  H01L27/1156 ,  H01L28/40 ,  H01L28/60 ,  H01L29/105 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。

公开(公告)号：US09064903B2

公开(公告)日：2015-06-23

申请号：US14172608

申请日：2014-02-04

Applicant: Texas Instruments Incorporated

Inventor： Allan T. Mitchell ,  Imran Mahmood Khan ,  Michael A. Wu

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/265 ,  H01L29/10 ,  H01L23/522 ,  H01L27/115 ,  H01L49/02 ,  H01L29/94

CPC classification number: H01L29/66825 ,  H01L21/2652 ,  H01L23/5223 ,  H01L27/11517 ,  H01L27/1156 ,  H01L28/40 ,  H01L28/60 ,  H01L29/105 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract translation: 集成电路中的模拟浮栅电极及其制造方法，其中捕获的电荷可以长时间存储。 模拟浮栅电极形成为多晶硅栅极电平，在其整个长度上掺杂n型，并且包括用作n沟道和p沟道MOS晶体管的栅电极的部分; 金属对多晶硅储存电容器的板; 以及一块多至多层隧道电容器。 p沟道MOS晶体管包括通过离子注入形成的掩埋沟道区，设置在其源区和漏区之间。 硅化物阻挡二氧化硅阻止在电极上形成硅化物包层，而集成电路中的其它多晶硅结构是硅化物包覆的。