公开(公告)号：US20250165416A1

公开(公告)日：2025-05-22

申请号：US18512210

申请日：2023-11-17

Applicant: Texas Instruments Incorporated

Inventor： Ashish Vanjari ,  Mohammed Arif ,  Shailesh Ganapat Ghotgalkar

IPC: G06F13/24 ,  G06F13/16

Abstract: In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.

公开(公告)号：US12119826B2

公开(公告)日：2024-10-15

申请号：US17849417

申请日：2022-06-24

Applicant: Texas Instruments Incorporated

Inventor： Srinivasa Chakravarthy ,  Prasanth Viswanathan Pillai ,  Mohammed Arif ,  Bhargov Bora

IPC: H03K5/00 ,  G06F1/06 ,  G06F11/263 ,  H03K21/02

CPC classification number: H03K5/00006 ,  G06F1/06 ,  G06F11/263 ,  H03K21/02

Abstract: An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

公开(公告)号：US20240405759A1

公开(公告)日：2024-12-05

申请号：US18805795

申请日：2024-08-15

Applicant: Texas Instruments Incorporated

Inventor： Srinivasa Chakravarthy ,  Prasanth Viswanathan Pillai ,  Mohammed Arif ,  Bhargov Bora

IPC: H03K5/00 ,  G06F1/06 ,  G06F11/263 ,  H03K21/02

Abstract: An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

公开(公告)号：US20220416771A1

公开(公告)日：2022-12-29

申请号：US17849417

申请日：2022-06-24

Applicant: Texas Instruments Incorporated

Inventor： Srinivasa Chakravarthy ,  Prasanth Viswanathan Pillai ,  Mohammed Arif ,  Bhargov Bora

IPC: H03K5/00 ,  H03K21/02 ,  G06F1/06

Abstract: An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.