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公开(公告)号:US20130233609A1
公开(公告)日:2013-09-12
申请号:US13787284
申请日:2013-03-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: STEVEN KUMMERL
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/49816 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H01L24/09 , H01L2224/08238 , H01L2924/0002 , H01L2924/15747 , H05K1/0306 , H05K1/115 , H05K3/0017 , Y10T29/49117 , H01L2924/00
Abstract: A method of forming interposers includes positioning a plurality of extruded metal wires across a first platten and second platten, which secures the extruded metal wires. A sealing material is added to sidewalls of a volume having the plurality of extruded metal wires within, with the first and second plattens as end plates to form a holding volume. The holding volume is filled with a filling material. The filling material is heated to a sufficient temperature to form a heat treated filled volume. After removing the sealing material, the heat treated filled volume is sawed into a plurality of slices having a predetermined thickness to form a plurality of interposer substrates having a plurality of feed-thru conducting features provided by the plurality of extruded metal wires.
Abstract translation: 一种形成插入件的方法包括将多个挤出的金属丝定位在第一平板和第二平板上,这固定了挤出的金属线。 将密封材料添加到具有多个挤压金属线的体积的侧壁中,其中第一和第二平板作为端板形成保持体积。 保持体积填充有填充材料。 将填充材料加热到足够的温度以形成经热处理的填充体积。 在去除密封材料之后,将经热处理的填充体积被锯切成具有预定厚度的多个切片,以形成具有由多个挤压金属丝提供的多个馈通导电特征的多个插入器基板。
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公开(公告)号:US20200083147A1
公开(公告)日:2020-03-12
申请号:US16123100
申请日:2018-09-06
Applicant: Texas Instruments Incorporated
Inventor: JO BITO , BENJAMIN STASSEN COOK , STEVEN KUMMERL
IPC: H01L23/495 , H01L23/498
Abstract: A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.
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公开(公告)号:US20240413058A1
公开(公告)日:2024-12-12
申请号:US18810024
申请日:2024-08-20
Applicant: Texas Instruments Incorporated
Inventor: JO BITO , BENJAMIN STASSEN COOK , STEVEN KUMMERL
IPC: H01L23/495 , H01L23/498
Abstract: A packaged semiconductor device includes an IC die having bump features that are coupled to bond pads flip chip attached to a custom LF. The custom LF includes metal structures including metal leads on at least 2 sides, and printed metal providing a printed LF portion including printed metal traces that connect to and extend inward from at least one of the metal leads over the dielectric support material that are coupled to FC pads configured for receiving the bump features including at least some of the printed metal traces coupled to the bond pads on the IC die. The IC die is flip chip mounted on the printed LF portion so that the bump features are connected to the FC pads.
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公开(公告)号:US20160163630A1
公开(公告)日:2016-06-09
申请号:US15000884
申请日:2016-01-19
Applicant: Texas Instruments Incorporated
Inventor: STEVEN KUMMERL
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49827 , H01L21/486 , H01L23/49816 , H01L23/49838 , H01L23/49866 , H01L23/49894 , H01L24/09 , H01L2224/08238 , H01L2924/0002 , H01L2924/15747 , H05K1/0306 , H05K1/115 , H05K3/0017 , Y10T29/49117 , H01L2924/00
Abstract: A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer.
Abstract translation: 半导体器件包括具有挤压的通孔和半导体管芯的插入件。 内插件包括具有多个通孔的基板。 介电衬垫衬在所述通孔上。 多个通过导电的特征由在所述电介质衬垫内的多个挤压金属线提供。 附接到所述插入件的半导体管芯。
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