公开(公告)号：US20240304223A1

公开(公告)日：2024-09-12

申请号：US18667059

申请日：2024-05-17

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  David J. Toops

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  H03K19/173

CPC classification number: G11C7/062 ,  G11C7/1069 ,  G11C7/12 ,  H03K19/1737

Abstract: A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

公开(公告)号：US20230267969A1

公开(公告)日：2023-08-24

申请号：US17877954

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  David J. Toops

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  H03K19/173

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C7/1069 ,  H03K19/1737

Abstract: A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

公开(公告)号：US11170864B2

公开(公告)日：2021-11-09

申请号：US16728975

申请日：2019-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suresh Balasubramanian ,  Stephen Wayne Spriggs ,  George B. Jamison

IPC: G11C17/00 ,  G11C17/18 ,  H03K17/687 ,  H03K17/693 ,  G11C17/16

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. The method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.

公开(公告)号：US20200265907A1

公开(公告)日：2020-08-20

申请号：US16729146

申请日：2019-12-27

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  Stephen Wayne Spriggs ,  George B Jamison

IPC: G11C17/18 ,  G11C17/16 ,  H03K3/356

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

公开(公告)号：US11145378B2

公开(公告)日：2021-10-12

申请号：US16729146

申请日：2019-12-27

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  Stephen Wayne Spriggs ,  George B Jamison

IPC: G11C17/00 ,  G11C17/18 ,  H03K3/356 ,  G11C17/16

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve performance while reading a one-time programmable memory. An example apparatus includes: a voltage boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, a third input coupled to a second output of the decoder; and a multiplexer including a first input coupled to the first output of the voltage boost circuit, a second input coupled to the second output of the voltage boost circuit, a third input coupled to an array of memory, and an output coupled to a sensing circuit.

公开(公告)号：US12027229B2

公开(公告)日：2024-07-02

申请号：US17877954

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  David J. Toops

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  H03K19/173

CPC classification number: G11C7/062 ,  G11C7/1069 ,  G11C7/12 ,  H03K19/1737

Abstract: A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

公开(公告)号：US20200265906A1

公开(公告)日：2020-08-20

申请号：US16728975

申请日：2019-12-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suresh Balasubramanian ,  Stephen Wayne Spriggs ,  George B. Jamison

IPC: G11C17/18 ,  G11C17/16 ,  H03K17/693 ,  H03K17/687

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed that improve performance while reading memory. An example method includes initializing an output of a of a sensing circuit to be a first logic high value, obtaining, from the memory, a first current corresponding to a memory bit stored in the memory, replicating the first current, determining whether the replicated first current is greater than a second current, and in response to determining that the replicated first current is greater than the second current, generating a second logic high value at the output of the sensing circuit.