公开(公告)号：US20170141101A1

公开(公告)日：2017-05-18

申请号：US15368958

申请日：2016-12-05

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L27/06 ,  H01L29/06 ,  H01L21/8249 ,  H01L29/45 ,  H01L29/417 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US09818740B2

公开(公告)日：2017-11-14

申请号：US15368958

申请日：2016-12-05

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L27/06 ,  H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/417 ,  H01L21/8249 ,  H01L27/092

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US20220140105A1

公开(公告)日：2022-05-05

申请号：US17087379

申请日：2020-11-02

Applicant: Texas Instruments Incorporated

Inventor： Zachary Ka Fai Lee ,  YuGuo Wang

IPC: H01L29/51 ,  H01L29/423 ,  H01L21/762

Abstract: A semiconductor device includes a Silicon-on-Insulator (SOI) substrate including a top device layer, a buried oxide (BOX) layer, and a bottom handle portion. A filled trench is lined with a trench dielectric layer that extends to at least the BOX layer, defining an inner and an outer portion of the device layer. A field effect transistor (FET) includes an inner portion, a source region having a source contact thereto and a drain region having a drain contact thereto, each doped a first doping type. A gate region has a gate contact that is separated from the inner portion by the trench dielectric. The source and drain region are separated by a body region doped a second doping type having a body contact.

公开(公告)号：US09548298B1

公开(公告)日：2017-01-17

申请号：US14942979

申请日：2015-11-16

Applicant: Texas Instruments Incorporated

Inventor： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC: H01L21/338 ,  H01L27/06 ,  H01L29/732 ,  H01L21/8238 ,  H01L21/8222

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

Abstract translation: 集成电路包括NMOS晶体管，PMOS晶体管和垂直双极晶体管。 垂直双极晶体管具有在本征基极的表面边界处具有至少25meV高的带势垒的本征基极，除了在与发射极的发射极 - 基极结之外，并且除了在与集电极的基极 - 集电极结之外。 本征碱可以被具有比本征碱更高的掺杂剂密度的外在碱基侧向包围，其中较高的掺杂剂密度在本征碱的侧表面提供带阻挡。 栅极可以设置在与发射极相邻的本征基极的顶表面边界上的栅极电介质层上。 栅极被配置为在栅极电介质层的正下方积聚本征基极，从而在本征基极的顶部表面边界提供带状屏障。