Secure Mechanism For Transmitting Counter Value In The Context Of Transmission Of A Synchronizing Signal In A Packet Network
    1.
    发明申请
    Secure Mechanism For Transmitting Counter Value In The Context Of Transmission Of A Synchronizing Signal In A Packet Network 有权
    用于在分组网络中的同步信号的传输的背景下发送计数器值的安全机制

    公开(公告)号:US20090073976A1

    公开(公告)日:2009-03-19

    申请号:US12225016

    申请日:2007-03-13

    IPC分类号: H04L12/56

    摘要: The invention concerns a device able for receiving packets in a packet communication network comprising at least two stations, characterized in that it includes: phase-locked loop, as well as means for: receiving packets containing samples of said network, said samples being derived from data sampled every Tech period, where Tech is derived from a time base synchronized on all the stations of said network and said samples being associated with incremental values predicting at least one sample, calculating, in case of interruption of packet reception, a prediction of a sample that should have been received, by adding an increment value to a received sample value. The invention also concerns a device for transmitting packets in a packet communication network.

    摘要翻译: 本发明涉及一种能够在包括至少两个站的分组通信网络中接收分组的设备,其特征在于,其包括:锁相环,以及用于:接收包含所述网络的采样的分组的装置,所述样本从 在每个技术期采样的数据,其中,技术来自在所述网络的所有站上同步的时基,并且所述样本与预测至少一个样本的增量值相关联,在分组接收中断的情况下,计算一个 通过向收到的样本值添加增量值,应该已经收到的样本。 本发明还涉及用于在分组通信网络中传送分组的设备。

    Generation and operation of a double timestamp for transmitting a synchronizing signal in a packet switching network
    2.
    发明授权
    Generation and operation of a double timestamp for transmitting a synchronizing signal in a packet switching network 有权
    用于在分组交换网络中发送同步信号的双时间戳的生成和操作

    公开(公告)号:US07903694B2

    公开(公告)日:2011-03-08

    申请号:US12225019

    申请日:2007-03-12

    IPC分类号: H04J3/06

    摘要: A device is disclosed for transmitting packets in a packet communication network comprising at least two stations, including in particular means for generating a first timestamp from a sampled value of a master counter, means for generating a second timestamp from a sampled value of a second counter synchronized on the at least two stations and means for transmitting jointly the two timestamps in the packet communication network. A device is further disclosed for receiving packets in a packet communication network, which uses the double timestamp generated by the transmitter device.

    摘要翻译: 公开了一种用于在包括至少两个站的分组通信网络中发送分组的设备,包括特别地用于从主计数器的采样值生成第一时间戳的装置,用于从第二计数器的采样值产生第二时间戳的装置 在至少两个站上同步,以及用于在分组通信网络中联合发送两个时间戳的装置。 还公开了一种用于在分组通信网络中接收分组的设备,其使用由发射机设备生成的双时间戳。

    Reduction in the acquisition duration of a phase-locked loop able to reconstitute a synchronisation signal transmitted over an IP network
    3.
    发明授权
    Reduction in the acquisition duration of a phase-locked loop able to reconstitute a synchronisation signal transmitted over an IP network 有权
    减少能够重建通过IP网络发送的同步信号的锁相环的采集持续时间

    公开(公告)号:US08223806B2

    公开(公告)日:2012-07-17

    申请号:US12733521

    申请日:2008-09-05

    IPC分类号: H04J3/06

    CPC分类号: H03L7/10

    摘要: The present invention relates to the domain of video equipment. More specifically, it concerns a reception device that comprises the means for: receiving packets containing samples, that come from data sampled every Tech period, where Tech is from a time base synchronized on all the stations of said network, regenerating a counting ramp having a count increment and a range value PCR_Modulus, using a phase-locked loop PLL1 that receives the samples and that delivers local samples every Tech period and a reconstituted clock, initializing, at every zero-crossing of the counting ramp, an image counter that is determined by the reconstituted clock. According to the invention, it comprises, further, means for determining the values of count increments.

    摘要翻译: 本发明涉及视频设备领域。 更具体地说,它涉及一种接收装置,其包括以下装置:接收包含样本的分组,来自每个技术周期采样的数据,其中,Tech来自在所述网络的所有站上同步的时基,重新生成具有 计数增量和范围值PCR_Modulus,使用接收采样的锁相环路PLL1,并且在每个技术周期传递本地采样,并且在计数斜坡的每个过零点处重新构建时钟,初始化,确定的图像计数器 由重建时钟。 根据本发明,其还包括用于确定计数增量的值的装置。

    Secure mechanism for transmitting counter value in the context of transmission of a synchronizing signal in a packet network
    4.
    发明授权
    Secure mechanism for transmitting counter value in the context of transmission of a synchronizing signal in a packet network 有权
    用于在分组网络中发送同步信号的上下文中发送计数器值的安全机制

    公开(公告)号:US08218577B2

    公开(公告)日:2012-07-10

    申请号:US12225016

    申请日:2007-03-13

    IPC分类号: H04J3/06

    摘要: An apparatus for transmitting and receiving packets in a packet switching network that includes at least two stations. The apparatus includes a phase-locked loop, as well as means for receiving packets containing samples of the network, the samples being derived from data sampled every Tech period, where Tech is derived from a time base synchronized on all the stations of the network and the samples being associated with incremental values predicting at least one sample, calculating, in case of interruption of packet reception, a prediction of a sample that should have been received, by adding an increment value to a received sample value.

    摘要翻译: 一种用于在包括至少两个站的分组交换网络中发送和接收分组的装置。 该装置包括锁相环,以及用于接收包含网络样本的分组的装置,样本是从每个技术周期采样的数据派生的,其中,Tech来自于在网络的所有站上同步的时基, 所述样本与预测至少一个样本的增量值相关联,在分组接收的中断的情况下,通过将接收到的样本值加上增量值来计算应该已经接收到的样本的预测。

    REDUCTION IN THE ACQUISITION DURATION OF A PHASE-LOCKED LOOP ABLE TO RECONSTITUTE A SYNCHRONISATION SIGNAL TRANSMITTED OVER AN IP NETWORK
    5.
    发明申请
    REDUCTION IN THE ACQUISITION DURATION OF A PHASE-LOCKED LOOP ABLE TO RECONSTITUTE A SYNCHRONISATION SIGNAL TRANSMITTED OVER AN IP NETWORK 有权
    在相位锁定环路的采集时间内减少以重新发送通过IP网络发送的同步信号

    公开(公告)号:US20100195674A1

    公开(公告)日:2010-08-05

    申请号:US12733521

    申请日:2008-09-05

    IPC分类号: H03D3/24 H04J3/06

    CPC分类号: H03L7/10

    摘要: The present invention relates to the domain of video equipment. More specifically, it concerns a reception device that comprises the means for: receiving packets containing samples, that come from data sampled every Tech period, where Tech is from a time base synchronised on all the stations of said network, regenerating a counting ramp having a count increment and a range value PCR_Modulus, using a phase-locked loop PLL1 that receives the samples and that delivers local samples every Tech period and a reconstituted clock, initialising, at every zero-crossing of the counting ramp, an image counter that is determined by the reconstituted clock. According to the invention, it comprises, further, means for determining the values of count increments.

    摘要翻译: 本发明涉及视频设备的领域。 更具体地说,它涉及一种接收装置,其包括以下装置:接收包含样本的分组,来自每个技术周期采样的数据,其中,Tech来自在所述网络的所有站上同步的时基,重新生成具有 计数增量和范围值PCR_Modulus,使用接收采样的锁相环路PLL1,并且在每个技术周期传送本地采样,并在计数斜坡的每个过零点处重新构建时钟,初始化,确定的图像计数器 由重建时钟。 根据本发明,其还包括用于确定计数增量的值的装置。

    Generating And Operating A Double Temporal Descriptor For Transmitting A Synchronizing Signal In A Packet Network
    6.
    发明申请
    Generating And Operating A Double Temporal Descriptor For Transmitting A Synchronizing Signal In A Packet Network 有权
    生成和操作用于在分组网络中发送同步信号的双时间描述符

    公开(公告)号:US20090034560A1

    公开(公告)日:2009-02-05

    申请号:US12225019

    申请日:2007-03-12

    IPC分类号: H04J3/06

    摘要: The invention concerns device for transmitting packets in a packet communication network comprising at least two stations, including in particular means for generating a first temporal descriptor from a sampled value of a master counter, means for generating a second temporal descriptor from a sampled value of a second counter synchronized on all the network stations and means for transmitting jointly the two temporal descriptors in the network. The invention also concerns a device for receiving packets in a packet communication network, which uses the double temporal descriptor generated by the transmitter device.

    摘要翻译: 本发明涉及用于在包括至少两个站的分组通信网络中传送分组的设备,包括特别地用于根据主计数器的采样值产生第一时间描述符的装置,用于根据主计数器的采样值产生第二时间描述符 在所有网络站上同步的第二计数器和用于在网络中联合发送两个时间描述符的装置。 本发明还涉及用于在分组通信网络中接收分组的设备,其使用由发射机设备生成的双时间描述符。

    Automatic compensation of a delay of a synchronization signal in a packet switching network
    7.
    发明授权
    Automatic compensation of a delay of a synchronization signal in a packet switching network 有权
    自动补偿分组交换网络中同步信号的延迟

    公开(公告)号:US08170013B2

    公开(公告)日:2012-05-01

    申请号:US12452056

    申请日:2008-06-06

    IPC分类号: H04L12/28

    摘要: The present invention relates to a sending device able to send packets in a network comprising at least two stations, the said device comprising means for extracting image pips on the basis of a synchronization signal, initializing an image counter on the basis of the image pips, initializing a counter every “m” zero-crossings of the image counter, the counter being regulated by a clock produced by the image counter, sampling the counter every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the said network; and sending packets containing the samples of the counter in the network. According to the invention, it comprises means for receiving packets containing samples sent by a station of the network as echo to the samples and when samples are received for: evaluating a duration of propagation of samples over an outward-return trip between the said device and the said station; determining a phase shift value Δφ on the basis of the duration of propagation; sending the phase shift value Δφ in the network.

    摘要翻译: 本发明涉及能够在包括至少两个站的网络中发送分组的发送设备,所述设备包括:用于基于同步信号提取图像点的装置,基于图像点初始化图像计数器; 在图像计数器的每个“m”过零点初始化计数器,计数器由图像计数器产生的时钟调节,每个周期Tsmp对计数器进行采样,其中Tsmp从在所述的所有的所有站的同步的时基发出 网络; 并在网络中发送包含计数器样本的数据包。 根据本发明,它包括用于接收包含由网络的站发送的样本的分组的分组作为对样本的回波的装置,以及当接收样本时:评估样本在所述装置与所述装置之间的向外返回行程的传播持续时间 所述车站; 确定相移值&Dgr;&phgr; 在传播的持续时间的基础上; 发送相移值&Dgr;&phgr; 在网络中。

    Device to transmit pulses over a packet-switched network
    8.
    发明申请
    Device to transmit pulses over a packet-switched network 失效
    通过分组交换网络传输脉冲的设备

    公开(公告)号:US20100226394A1

    公开(公告)日:2010-09-09

    申请号:US12455549

    申请日:2009-06-03

    IPC分类号: H04J3/07

    CPC分类号: H04N7/56 H04J3/0664

    摘要: The present invention relates to a device able to receive packets circulating in a packet communication network, said device comprising: the means to receive packets from said network, said packets comprising samples coming from a sampling of a counting ramp having a range EX according to a sampling clock, said counting ramp being timed by a clock with a period of T_VID, said means extracting said samples from received packets, the means to regenerate counting ramps with a range EX, the means (PLL) receiving the samples and also delivering local samples of counting ramps realised according to sampling clock and a reconstituted clock with a period T_VID, the counting ramps being timed by the clock, the means to produce counting ramps timed by the clock and having a range EX_I where EX=m.EX_I, m being a whole number necessarily greater than 1, the counting ramps being set to zero at each passage of the counting ramp by a fixed whole number M where 0

    摘要翻译: 本发明涉及一种能够接收在分组通信网络中循环的分组的设备,所述设备包括:从所述网络接收分组的装置,所述分组包括来自具有根据以下的范围EX的计数斜坡的采样的样本 采样时钟,所述计数斜坡由周期为T_VID的时钟定时,所述装置从接收到的分组提取所述样本,用于重新产生具有范围EX的计数斜坡的装置,所述装置(PLL)接收采样并且还递送局部采样 根据采样时钟实现的斜坡计数和具有周期T_VID的重构时钟,计时斜坡由时钟定时,产生由时钟定时的计数斜坡的装置,并具有范围EX_I,其中EX = m.EX_I,m为 整数必须大于1,在计数斜坡每通过一个固定的整数M,其中0

    PLL LOOP ABLE TO RECOVER A SYNCHRONISATION CLOCK RHYTHM COMPRISING A TEMPORAL DISCONTINUITY
    9.
    发明申请
    PLL LOOP ABLE TO RECOVER A SYNCHRONISATION CLOCK RHYTHM COMPRISING A TEMPORAL DISCONTINUITY 有权
    PLL环路可以恢复包含时钟不连续性的同步时钟周期

    公开(公告)号:US20100214477A1

    公开(公告)日:2010-08-26

    申请号:US12733495

    申请日:2008-09-05

    IPC分类号: H04N5/04

    摘要: The present invention relates to the domain of video equipment. It relates to a phase-locked loop able to recover the timing of a synchronization signal comprising a temporal discontinuity of a maximum amplitude equal to PCR_Modulus, the loop comprising:a sample comparator comparing the samples and the local samples of a synthesised signal,means for producing the synthesised signal from a corrected signal,a corrector receiving a comparison result delivered by the comparison means and delivering the corrected signal, According to the invention, the comparison means comprises the means to determine a difference in value between the local samples and the samples of the synchronisation signal and in that the comparison result has a value that depends on the value ε and on the difference between the value ε and the value PCR_Modulus/2.

    摘要翻译: 本发明涉及视频设备的领域。 它涉及能够恢复包括等于PCR_Modulus的最大幅度的时间不连续性的同步信号的定时的锁相环,该环路包括:比较样本和合成信号的局部采样的采样比较器, 根据本发明,比较装置包括用于确定局部样本与样本之间的值之差的装置,其中,所述比较装置包括: 的同步信号,并且比较结果具有取决于值&egr的值; 和价值与价值之间的差异 值为PCR_Modulus / 2。

    PRECESION/SPEED COMPROMISE OF A SYNCHRONIZATION SIGNAL RECEPTION DEVICE
    10.
    发明申请
    PRECESION/SPEED COMPROMISE OF A SYNCHRONIZATION SIGNAL RECEPTION DEVICE 有权
    同步信号接收设备的优先级/速度压缩率

    公开(公告)号:US20100135333A1

    公开(公告)日:2010-06-03

    申请号:US12452051

    申请日:2008-06-06

    IPC分类号: H04J3/06

    摘要: The present invention relates to a reception device able to receive packets in a communication network comprising at least two stations. The device comprises means for: receiving packets containing samples of the network which originate from data sampled every period Tsmp, where Tsmp emanates from a time base synchronized on all the stations of the said network; regenerating a counting ramp with the aid of a loop receiving the samples and furthermore delivering local samples every period Tsmp and a clock; the phase-locked loop comprises: a samples comparator comparing the samples and the local samples and delivering an error signal; a corrector receiving the signal and delivering a corrected error signal, the corrector having a static gain equal to 1; a digital oscillator receiving the corrected error signal and delivering the clock, which has a frequency dependent on the signal and is proportional to a gain. According to the invention, the phase-locked loop comprises, furthermore, a gain adjustment device which determines a gain value as a function of the error signal.

    摘要翻译: 本发明涉及能够在包括至少两个站的通信网络中接收分组的接收装置。 该设备包括:用于:接收包含网络样本的分组,该分组源自每个周期Tsmp采样的数据,其中Tsmp从在所述网络的所有站同步的时基发出; 借助于接收样本的环路再生计数斜坡,并且每个周期Tsmp和时钟传送局部样本; 所述锁相环包括:采样比较器,比较所述采样和所述局部采样并传送误差信号; 校正器接收信号并传送校正的误差信号,校正器具有等于1的静态增益; 接收经校正的误差信号并传送时钟的数字振荡器,其具有取决于信号的频率并与增益成比例。 根据本发明,锁相环还包括一个增益调节装置,其确定作为误差信号的函数的增益值。