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公开(公告)号：US08080451B2
公开(公告)日：2011-12-20
申请号：US12684551
申请日：2010-01-08
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Solutions for fabricating a semiconductor structure. One embodiment includes a method for fabricating a semiconductor structure, the method including: forming a first dielectric structure on a substrate, the first dielectric structure including silicon nitride (Si3N4); forming a second dielectric structure in proximity to the first dielectric structure; and growing a non-epitaxial thin film from a surface of the first dielectric structure; wherein the growing includes using a combination of precursor, carrier and etchant with a ratio among the precursor, carrier, and etchant being adjusted for selective growth of the thin film on the surface, and wherein the thin film includes one selected from a group consisting of: a monocrystalline material, an amorphous material, a polycrystalline material and a combination thereof.
摘要翻译： 制造半导体结构的解决方案。 一个实施例包括一种用于制造半导体结构的方法，所述方法包括：在衬底上形成第一电介质结构，所述第一电介质结构包括氮化硅（Si 3 N 4）; 在所述第一电介质结构附近形成第二电介质结构; 以及从所述第一电介质结构的表面生长非外延薄膜; 其中所述生长包括使用前体，载体和蚀刻剂的组合，前体，载体和蚀刻剂之间的比例被调节用于表面上的薄膜的选择性生长，并且其中所述薄膜包括选自以下的一种： ：单晶材料，非晶材料，多晶材料及其组合。
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公开(公告)号：US07687804B2
公开(公告)日：2010-03-30
申请号：US11970592
申请日：2008-01-08
IPC分类号： H01L29/04 , H01L31/20 , H01L31/036 , H01L31/0376
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.
摘要翻译： 制造具有设置在半导体结构的基板的表面上的非外延薄膜的半导体结构的方法; 并且公开了由其形成的半导体结构。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。
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公开(公告)号：US20090173941A1
公开(公告)日：2009-07-09
申请号：US11970592
申请日：2008-01-08
IPC分类号： H01L29/04 , H01L21/205
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Methods of fabricating a semiconductor structure with a non-epitaxial thin film disposed on a surface of a substrate of the semiconductor structure; and semiconductor structures formed thereof are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.
摘要翻译： 制造具有设置在半导体结构的基板的表面上的非外延薄膜的半导体结构的方法; 并且公开了由其形成的半导体结构。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。
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公开(公告)号：US20100112762A1
公开(公告)日：2010-05-06
申请号：US12684551
申请日：2010-01-08
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/66545 , H01L21/0237 , H01L21/02422 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/0262 , H01L21/02636 , H01L21/0332 , H01L21/0337 , H01L21/32139 , H01L21/76224 , H01L29/165 , H01L29/41783 , H01L29/66553
摘要： Methods of fabricating a semiconductor structure with a non- epitaxial thin film disposed on a surface of a substrate of the semiconductor structure are disclosed. The methods provide selective non-epitaxial growth (SNEG) or deposition of amorphous and/or polycrystalline materials to form a thin film on the surface thereof. The surface may be a non-crystalline dielectric material or a crystalline material. The SNEG on non-crystalline dielectric further provides selective growth of amorphous/polycrystalline materials on nitride over oxide through careful selection of precursors-carrier-etchant ratio. The non-epitaxial thin film forms resultant and/or intermediate semiconductor structures that may be incorporated into any front-end-of-the-line (FEOL) fabrication process. Such resultant/intermediate structures may be used, for example, but are not limited to: source-drain fabrication; hardmask strengthening; spacer widening; high-aspect-ratio (HAR) vias filling; micro-electro-mechanical-systems (MEMS) fabrication; FEOL resistor fabrication; lining of shallow trench isolations (STI) and deep trenches; critical dimension (CD) tailoring and claddings.
摘要翻译： 公开了制造具有设置在半导体结构的衬底的表面上的非外延薄膜的半导体结构的方法。 该方法提供非晶和/或多晶材料的选择性非外延生长（SNEG）或沉积以在其表面上形成薄膜。 表面可以是非结晶介电材料或结晶材料。 非结晶电介质上的SNEG还通过仔细选择前体载体 - 蚀刻剂比例，进一步提供非晶/多晶材料对氧化物上的氮化物的选择性生长。 非外延薄膜形成可并入到任何前端（FEOL）制造工艺中的所得和/或中间半导体结构。 这样的合成/中间结构可以用于例如但不限于：源极 - 漏极制造; 硬掩模强化; 间隔加宽; 高纵横比（HAR）通孔填充; 微电子机械系统（MEMS）制造; FEOL电阻制造; 浅沟槽隔离（STI）和深沟槽衬砌; 临界尺寸（CD）裁剪和包层。
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5.发明授权Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering 有权具有高K金属栅极集成和SiGe沟道工程的PMOS器件的方法和结构公开(公告)号：US08575655B2
公开(公告)日：2013-11-05
申请号：US13431328
申请日：2012-03-27
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/66
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。
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6.发明申请METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING 有权具有高K金属栅组合和SiGe通道工程的PMOS器件的方法和结构公开(公告)号：US20120181631A1
公开(公告)日：2012-07-19
申请号：US13431328
申请日：2012-03-27
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
IPC分类号： H01L29/78
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。
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公开(公告)号：US20080026516A1
公开(公告)日：2008-01-31
申请号：US11459730
申请日：2006-07-25
IPC分类号： H01L21/8234
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
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8.发明申请METHOD AND STRUCTURE FOR PMOS DEVICES WITH HIGH K METAL GATE INTEGRATION AND SiGe CHANNEL ENGINEERING 失效具有高K金属栅组合和SiGe通道工程的PMOS器件的方法和结构公开(公告)号：US20100200937A1
公开(公告)日：2010-08-12
申请号：US12367759
申请日：2009-02-09
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
摘要翻译： 公开了通过使用SiGe通道来改变衬底的功函数的各种技术，其又有利于改变p型金属氧化物半导体场效应晶体管（pMOSFET）的带隙。 在各种技术中，SiGe膜包括在更高掺杂的SiGe区域上方的低掺杂SiGe区域，以允许pMOSFET器件的适当阈值电压（Vt），同时防止随后的清洁和处理期间SiGe膜的点蚀，粗糙度和变薄 被提供。
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9.发明申请RAISED STI STRUCTURE AND SUPERDAMASCENE TECHNIQUE FOR NMOSFET PERFORMANCE ENHANCEMENT WITH EMBEDDED SILICON CARBON 有权用于具有嵌入式硅碳的NMOSFET性能增强的提高的结构和超级散射技术公开(公告)号：US20080128712A1
公开(公告)日：2008-06-05
申请号：US12028191
申请日：2008-02-08
IPC分类号： H01L27/092 , H01L29/778
CPC分类号： H01L21/823864 , H01L21/76224 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/165 , H01L29/66628 , H01L29/7843 , H01L29/7848
摘要： An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.
摘要翻译： 通过过度填充由晶体管栅极结构形成的间隙或沟槽，实现了通过向NFET的沟道区域施加张力来有效地增加电子迁移率的具有超过1％的取代碳含量的嵌入式硅碳（Si：C） 用Si：C，并在超级马赛克法中抛光将Si：C蚀刻到升高的栅极结构的表面或之下，即使在晶体管源极和漏极之上的选定区域中仅保留Si：C，即使能够沉积 具有足够高的替代碳含量的Si：C固有地是非选择性的。
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10.发明授权公开(公告)号：US08440547B2
公开(公告)日：2013-05-14
申请号：US12367759
申请日：2009-02-09
申请人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
发明人： Stephen W. Bedell , Ashima B. Chakravarti , Michael P. Chudzik , Judson R. Holt , Dominic J. Schepis
CPC分类号： H01L29/1054 , H01L21/0237 , H01L21/02532 , H01L21/02612 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.
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