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公开(公告)号：US20130070921A1
公开(公告)日：2013-03-21
申请号：US13639181
申请日：2011-04-12
IPC分类号： H04M1/274
CPC分类号： H04L41/0803 , H04L41/0213 , H04L41/22 , H04L65/1026 , H04M3/42187
摘要： A method functions to resolve conflicts between wireless digital telephony and traditional analog telephony when an automatic telephone number dialer is concurrently used in a gateway. The method acts to prioritize telephone calls that operate using one telephone line when a single analog telephone line interfaces with an automatic telephone dialer and an analog telephone set in a system that also operates with a wireless digital telephone interface. The method includes detecting if an active call is present and determines if the telephone number being dialed is of higher priority than the active call. The highest priority call is placed or preserved according to the highest priority regardless of the source of the call in the system.
摘要翻译： 当在网关中同时使用自动电话号码拨号器时，一种方法用于解决无线数字电话与传统模拟电话之间的冲突。 该方法用于在单个模拟电话线路与自动电话拨号器和系统中的模拟电话机接口同时使用无线数字电话接口进行操作时，优先使用一条电话线进行操作的电话呼叫。 该方法包括检测是否存在活动呼叫，并且确定被拨打的电话号码是否比活动呼叫更高优先级。 无论系统中的呼叫来源如何，最高优先级呼叫都将按照最高优先级进行放置或保留。
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公开(公告)号：US06633344B1
公开(公告)日：2003-10-14
申请号：US09584148
申请日：2000-05-31
IPC分类号： H04N964
CPC分类号： H04N7/012 , H04N5/4401 , H04N5/46 , H04N9/641 , H04N21/440218 , H04N21/4435
摘要： A memory management process for buffering progressive, interlaced, CCIR 601/656 compliant, and MPEG compliant video signals in a video memory that is partitioned into first and second buffers. The process includes identifying the format of a received video signal, buffering the received video signal in the video memory in accordance with a standard buffering mode if the video signal is in an interlaced, CCIR 601/656 compliant, or MPEG compliant format, and buffering the received video signal in the video memory in accordance with an override buffering mode if the video signal is in a progressive format such as a 240p signal generated by a game console, VCR, cable text generator, and the like.
摘要翻译： 一种存储器管理过程，用于在被划分成第一和第二缓冲器的视频存储器中缓冲逐行，隔行扫描CCIR 601/656兼容和MPEG兼容视频信号。 该过程包括识别所接收的视频信号的格式，如果视频信号是隔行扫描CCIR 601/656兼容或MPEG兼容格式，则根据标准缓冲模式来缓冲接收的视频信号在视频存储器中，并且缓冲 如果视频信号是诸如由游戏机，VCR，电缆文本生成器等产生的240p信号的逐行格式，则根据超控缓冲模式在视频存储器中接收的视频信号。
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公开(公告)号：US20170094367A1
公开(公告)日：2017-03-30
申请号：US14864109
申请日：2015-09-24
申请人： Michael Evan Crabb
发明人： Michael Evan Crabb
IPC分类号： H04N21/488 , H04N21/43 , H04N21/61 , H04N21/81 , H04N21/462 , H04N21/41 , H04N21/431
CPC分类号： H04N21/4884 , H04N21/4122 , H04N21/4126 , H04N21/4307 , H04N21/4312 , H04N21/4622 , H04N21/6125 , H04N21/8133
摘要： Text data associated with multimedia content is transmitted to a mobile device while the multimedia content is shown on a separate network and remote apparatus. The mobile device requests the text data associated with the multimedia content and can optionally send hints to help determine which multimedia content text should be transmitted. The received text data is rendered in a scrollable, temporal representation, allowing recall of prior text associated with past multimedia content images.
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公开(公告)号：US06894726B2
公开(公告)日：2005-05-17
申请号：US10190282
申请日：2002-07-05
CPC分类号： H04N7/0132 , H04N7/012 , Y10S348/911
摘要： A combined de-interlacing and frame doubling system (114, 114′ and 114″) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116′ and 116″) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140′1, 1140″) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.
摘要翻译： 组合的去隔行和帧倍增系统（114,114'和114“）有利地用于以现场速率的两倍将当前视频数据的连续行去隔行，以产生适于在显示设备上显示的输出比特流， 利用逐行扫描。 根据本原理的去隔行和帧倍增系统包括用于存储具有规定场速的隔行扫描视频的至少一帧的帧存储机构（116,116'和116“）。 至少一个去隔行电路（1140,1401,1140“，1140”）以至少两个视场数据从存储器机构以 至少两次用于在场周期的一半中执行完全去隔行扫描功能的场速率，以产生用于在显示装置处接收的渐进的帧双倍信号。
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公开(公告)号：US06573944B1
公开(公告)日：2003-06-03
申请号：US09562455
申请日：2000-05-02
IPC分类号： H04N504
CPC分类号： H04N5/126
摘要： A horizontal synchronizing system, comprising: a source of a horizontal synchronizing signal; a source of first and second higher frequency horizontal drive signals; a phase detector for generating a first control voltage responsive to the horizontal synchronizing signal and the first horizontal drive signal; a source of a second control signal; and, a switch for selectively supplying the first control signal to the source of the drive signals for a phase-locked mode of operation at the first higher frequency and supplying the second control signal to the source of the drive signals for a phase-unlocked mode of operation at the second higher frequency.
摘要翻译： 一种水平同步系统，包括：水平同步信号源; 第一和第二较高频率水平驱动信号的源; 相位检测器，用于响应于水平同步信号和第一水平驱动信号产生第一控制电压; 第二控制信号的源; 以及开关，用于选择性地将第一控制信号提供给驱动信号的源，以进行第一较高频率的锁相操作模式，并将第二控制信号提供给驱动信号的源以进行相位解锁模式 的运行在第二个更高的频率。
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公开(公告)号：US07468754B2
公开(公告)日：2008-12-23
申请号：US11036920
申请日：2005-01-14
CPC分类号： H04N7/0132 , H04N7/012 , Y10S348/911
摘要： A combined de-interlacing and frame doubling system (114, 114′ and 114″) advantageously serves to de-interlace successive lines of Present Field Video data at twice the field rate to yield an output bit stream suitable for display on display device that utilizes progressive scanning. The de-interlacing and frame doubling system in accordance with present principles includes a frame memory mechanism (116, 116′ and 116″) for storing at least one frame of interlaced video having a prescribed field rate. At least one de-interlacing circuit (11401, 1140′1, 1140″) pulls at least two fields of video data from the memory mechanism at a rate of at least twice the field rate for performing a full de-interlacing function in half of a field period to generate the a progressive, frame doubled signal for receipt at the display device.
摘要翻译： 组合的去隔行和帧倍增系统（114,114'和114“）有利地用于以现场速率的两倍将当前视频数据的连续行去隔行，以产生适于在显示设备上显示的输出比特流， 利用逐行扫描。 根据本原理的去隔行和帧倍增系统包括用于存储具有规定场速的隔行扫描视频的至少一帧的帧存储机构（116,116'和116“）。 至少一个去隔行电路（11401,1140'1,1140“）以至少两倍于场速率的速率从存储器机构拉出至少两个视频数据场，用于执行一半的完全去隔行功能 以产生用于在显示设备处接收的渐进的帧双倍信号。
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公开(公告)号：US07312830B2
公开(公告)日：2007-12-25
申请号：US10451606
申请日：2001-12-18
CPC分类号： H04N7/012 , H04N5/06 , H04N5/4401 , H04N21/440218
摘要： A method of converting interlaced video to progressive video can include a series of steps. The method can include receiving a video signal representative of at least one picture and determining whether the picture is progressive. If the picture is progressive, a vertical synchronization signal is modified to create an association with a first field of the picture. Accordingly, a progressive video signal can be converted to an interlaced video signal associated with the vertical synchronization signal and the interlaced video signal can then be converted to a progressive video signal in correspondence with modifications made to the vertical synchronization signal.
摘要翻译： 将隔行扫描视频转换成逐行视频的方法可以包括一系列步骤。 该方法可以包括接收表示至少一张照片的视频信号，并确定图像是否是渐进式的。 如果图像是渐进的，则修改垂直同步信号以创建与图像的第一场的关联。 因此，逐行视频信号可以转换成与垂直同步信号相关联的隔行扫描视频信号，并且隔行扫描视频信号然后可以根据对垂直同步信号的修改而被转换为逐行视频信号。
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公开(公告)号：US06420918B2
公开(公告)日：2002-07-16
申请号：US09957928
申请日：2001-09-21
IPC分类号： H03L706
摘要： A phase locked loop, comprising: a controllable oscillator requiring a control signal having a given bias voltage for generating a clock signal; an integrator for developing the control signal; a source of an external synchronizing signal; first and second voltage sources defining a voltage potential related to the given bias voltage; a first switch coupled to the first and second voltage sources and responsive to the clock signal for developing a regenerated clock signal having a peak to peak voltage determined by the voltage potential; and, a second switch responsive to the external synchronizing signal for periodically sampling portions of the regenerated clock signal and coupling the sampled portions to the integrator, the sampled portions charging and discharging the integrator to generate the control signal with a large enough magnitude to provide the given bias voltage, said first and second switches forming a phase detector.
摘要翻译： 一种锁相环路，包括：可控振荡器，其需要具有用于产生时钟信号的给定偏置电压的控制信号; 用于开发控制信号的积分器; 外部同步信号源; 第一和第二电压源限定与给定偏置电压相关的电压; 第一开关，其耦合到所述第一和第二电压源，并且响应于所述时钟信号，用于开发具有由所述电压电位确定的峰峰值电压的再生时钟信号; 以及响应于外部同步信号的第二开关，用于周期性地对再生的时钟信号的部分采样并将采样部分耦合到积分器，采样部分对积分器进行充电和放电以产生足够大的控制信号，以提供 给定的偏置电压，所述第一和第二开关形成相位检测器。
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