Technique for forming recessed sidewall spacers for a polysilicon line
    1.
    发明申请
    Technique for forming recessed sidewall spacers for a polysilicon line 有权
    用于形成多晶硅线路的凹陷侧壁间隔物的技术

    公开(公告)号:US20050026380A1

    公开(公告)日:2005-02-03

    申请号:US10786401

    申请日:2004-02-25

    摘要: In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.

    摘要翻译: 在形成复杂的场效应晶体管的双间隔或多间隔方法中,栅极电极的上侧壁部分可以在外间隔元件的凹陷期间被有效地暴露,因为外间隔件基本上由相同的材料组成 作为衬垫材料。 因此,用于凹陷外侧壁间隔件的各向异性蚀刻工艺还有效地去除了上侧壁部分上的衬垫残留物,并为难熔金属提供了增加的扩散路径。 此外,可以通过相应地控制用于去除氧化物残余物的各向同性蚀刻工艺来增加漏极和源极区域上的硅化物区域的横向延伸。

    Technique for forming recessed sidewall spacers for a polysilicon line
    2.
    发明授权
    Technique for forming recessed sidewall spacers for a polysilicon line 有权
    用于形成多晶硅线路的凹陷侧壁间隔物的技术

    公开(公告)号:US07005358B2

    公开(公告)日:2006-02-28

    申请号:US10786401

    申请日:2004-02-25

    IPC分类号: H01L21/336

    摘要: In a double-spacer or multi-spacer approach to the formation of sophisticated field effect transistors, an upper sidewall portion of a gate electrode may be effectively exposed during recessing of an outer spacer element, since the outer spacer is substantially comprised of the same material as the liner material. Consequently, the anisotropic etch process for recessing the outer sidewall spacer also efficiently removes liner residues on the upper sidewall portion and provides an increased diffusion path for a refractory metal. Additionally, the lateral extension of the silicide regions on the drain and source area may be increased by correspondingly controlling an isotropic etch process for removing oxide residues.

    摘要翻译: 在形成复杂的场效应晶体管的双间隔或多间隔方法中,栅极电极的上侧壁部分可以在外间隔元件的凹陷期间被有效地暴露,因为外间隔件基本上由相同的材料组成 作为衬垫材料。 因此,用于凹陷外侧壁间隔件的各向异性蚀刻工艺还有效地去除了上侧壁部分上的衬垫残留物,并为难熔金属提供了增加的扩散路径。 此外,可以通过相应地控制用于去除氧化物残余物的各向同性蚀刻工艺来增加漏极和源极区域上的硅化物区域的横向延伸。

    Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique
    4.
    发明授权
    Technique for forming a spacer for a line element by using an etch stop layer deposited by a highly directional deposition technique 有权
    通过使用通过高度定向沉积技术沉积的蚀刻停止层来形成用于线元件的间隔物的技术

    公开(公告)号:US07109086B2

    公开(公告)日:2006-09-19

    申请号:US10987827

    申请日:2004-11-12

    IPC分类号: H01L21/336

    摘要: The present invention provides a technique that enables the formation of a recessed spacer element by using an anisotropically deposited etch stop layer. Accordingly, in subsequent cleaning processes, material residues of the etch stop layer may be efficiently removed from upper sidewall portions of a line element, thereby increasing the available area for a diffusion path in a subsequent silicidation process. The anisotropic deposition of the etch stop layer may be accomplished by high density plasma enhanced CVD or by directional sputter techniques.

    摘要翻译: 本发明提供一种能够通过使用各向异性沉积的蚀刻停止层形成凹陷间隔元件的技术。 因此,在随后的清洗过程中,可以有效地从线元件的上侧壁部分去除蚀刻停止层的材料残留物,从而增加随后的硅化工艺中扩散路径的可用面积。 蚀刻停止层的各向异性沉积可以通过高密度等离子体增强CVD或定向溅射技术来实现。

    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers
    6.
    发明申请
    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers 有权
    提高氮化硅层的晶片到晶片厚度均匀性的方法

    公开(公告)号:US20050026434A1

    公开(公告)日:2005-02-03

    申请号:US10881932

    申请日:2004-06-30

    摘要: Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/or the chamber pressure before and after the actual deposition step, the process conditions may be more effectively stabilized, thereby reducing process variations, even after non-deposition phases of the deposition tool, such as a preceding plasma clean process or an idle period of the tool.

    摘要翻译: 在沉积氮化硅层的过程中,可以显着改善晶片对晶片的厚度均匀性,因为反应物的流速和室压力在沉积循环期间是变化的。 通过相应地适应实际沉积步骤之前和之后的流速和/或室压力,可以更有效地稳定工艺条件,从而即使在沉积工具的非沉积阶段(例如先前的等离子体)之后也减少工艺变化 清洁过程或工具的空闲期间。

    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers
    7.
    发明授权
    Method of improving the wafer-to-wafer thickness uniformity of silicon nitride layers 有权
    提高氮化硅层的晶片到晶片厚度均匀性的方法

    公开(公告)号:US08084088B2

    公开(公告)日:2011-12-27

    申请号:US10881932

    申请日:2004-06-30

    IPC分类号: C23C16/00

    摘要: Wafer-to-wafer thickness uniformity may be improved significantly in a process for depositing a silicon nitride layer in that the flow rate of the reactant and the chamber pressure are varied during a deposition cycle. By correspondingly adapting the flow rate and/or the chamber pressure before and after the actual deposition step, the process conditions may be more effectively stabilized, thereby reducing process variations, even after non-deposition phases of the deposition tool, such as a preceding plasma clean process or an idle period of the tool.

    摘要翻译: 在沉积氮化硅层的过程中,可以显着改善晶片对晶片的厚度均匀性,因为反应物的流速和室压力在沉积循环期间是变化的。 通过相应地适应实际沉积步骤之前和之后的流速和/或室压力,可以更有效地稳定工艺条件,从而即使在沉积工具的非沉积阶段(例如先前的等离子体)之后也减少工艺变化 清洁过程或工具的空闲期间。

    METHOD FOR FORMING A TUNGSTEN INTERCONNECT STRUCTURE WITH ENHANCED SIDEWALL COVERAGE OF THE BARRIER LAYER
    8.
    发明申请
    METHOD FOR FORMING A TUNGSTEN INTERCONNECT STRUCTURE WITH ENHANCED SIDEWALL COVERAGE OF THE BARRIER LAYER 失效
    用于形成具有增强的障碍层的覆盖层的隧道互连结构的方法

    公开(公告)号:US20070077749A1

    公开(公告)日:2007-04-05

    申请号:US11423900

    申请日:2006-06-13

    IPC分类号: H01L21/4763

    摘要: By performing a re-sputter process during the formation of a barrier layer for a contact opening in a tungsten-based process, the reliability of the tungsten deposition, as well as the performance of the resulting contact plug, may be enhanced. During the re-sputtering process, a thickness of the titanium-based barrier layer may be reduced at the contact bottom, while at the same time the material is re-condensed on critical lower sidewall portions of the contact opening.

    摘要翻译: 通过在形成钨基工艺中的接触开口的阻挡层的过程中进行再溅射工艺,可以提高钨沉积的可靠性以及所得到的接触塞的性能。 在再溅射过程中,钛基阻挡层的厚度可以在接触底部减小,同时材料在接触开口的临界下侧壁部分上再凝结。

    SEMICONDUCTOR DEVICE COMPRISING COPPER-BASED CONTACT PLUG AND A METHOD OF FORMING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE COMPRISING COPPER-BASED CONTACT PLUG AND A METHOD OF FORMING THE SAME 审中-公开
    包含基于铜箔的接触片的半导体器件及其形成方法

    公开(公告)号:US20070096221A1

    公开(公告)日:2007-05-03

    申请号:US11427206

    申请日:2006-06-28

    IPC分类号: H01L23/52 H01L21/44

    摘要: By providing a tungsten nitride barrier layer for a contact plug, well-approved copper-based via formation techniques may be used to form a highly conductive contact plug, thereby significantly reducing the series resistance compared to conventional tungsten-based contact plugs. The tungsten nitride barrier layer may be deposited by ALD techniques, which exhibit superior step coverage and thus allow a reliable coverage of exposed surfaces of the contact opening, thereby providing the potential for using copper or copper alloys even in the vicinity of highly sensitive device areas of circuit elements, such as transistors and the like.

    摘要翻译: 通过提供用于接触插塞的氮化钨阻挡层,可以使用良好认可的铜基通孔形成技术来形成高导电性接触插塞,从而与传统的钨基接触插塞相比显着降低串联电阻。 氮化钨阻挡层可以通过ALD技术沉积,其表现出优异的台阶覆盖率,从而允许接触开口的暴露表面的可靠覆盖,从而提供即使在高敏感器件区域附近使用铜或铜合金的潜力 的电路元件,例如晶体管等。