公开(公告)号：US20050002221A1

公开(公告)日：2005-01-06

申请号：US10902450

申请日：2004-07-29

申请人： Tie Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Jiang

发明人： Tie Wu ,  Chien-Chang Huang ,  Yu-Wei Ting ,  Bo Jiang

IPC分类号： G11C8/14 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/02 ,  G11C11/24

CPC分类号： H01L27/10861 ,  G11C8/14 ,  H01L22/34 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10891

摘要： A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.

摘要翻译： 用于验证覆盖DRAM的深沟槽电容器的字线结构的位置的测试键。 测试键被沉积在晶片的划线区域中。 深沟槽电容器沉积在划线区域并具有掩埋板。 在划线中沉积矩形字线并覆盖深沟槽电容器的一部分，并且在深沟槽上方沉积两条经过的字线。 第一掺杂区域和第二掺杂区域分别沉积在矩形字线和第一通过字线之间以及矩形字线和第二通过字线之间。 第一插头，第二插头和第三插头分别耦合到第一掺杂区域，第二掺杂区域和掩埋板。

公开(公告)号：US20050184289A1

公开(公告)日：2005-08-25

申请号：US11096836

申请日：2005-03-30

申请人： Tie Wu ,  Chien-Chang Huang ,  Bo Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

发明人： Tie Wu ,  Chien-Chang Huang ,  Bo Jiang ,  Yu-Wei Ting ,  Chin-Ling Huang

IPC分类号： G11C29/36 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  H01L21/66 ,  H01L23/58 ,  H01L29/10

CPC分类号： H01L27/10876 ,  G11C11/401 ,  G11C29/36 ,  G11C2029/5002 ,  H01L22/34 ,  H01L27/10841

摘要： A test device and method for detecting alignment of active areas and memory cell structures in DRAM devices with vertical transistors. In the test device, parallel first and second memory cell structures disposed in the scribe line region, each has a deep trench capacitor and a transistor structure. An active area is disposed between the first and second memory cell structures. The active area overlaps the first and second memory cell structures by a predetermined width. First and second conductive pads are disposed on both ends of the first memory cell structures respectively, and third and fourth conductive pads are disposed on both ends of the first memory cell structures respectively.

摘要翻译： 一种用于检测具有垂直晶体管的DRAM器件中的有源区和存储单元结构的对准的测试装置和方法。 在测试装置中，设置在划线区域中的并行第一和第二存储单元结构各自具有深沟槽电容器和晶体管结构。 有源区域设置在第一和第二存储单元结构之间。 活动区域与第一和第二存储单元结构重叠预定宽度。 第一和第二导电焊盘分别设置在第一存储单元结构的两端，第三和第四导电焊盘分别设置在第一存储单元结构的两端。