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    Memory latency and bandwidth optimizations
    5.
    发明授权
    Memory latency and bandwidth optimizations 失效
    内存延迟和带宽优化

    公开(公告)号：US07194577B2

    公开(公告)日：2007-03-20

    申请号：US10652943

    申请日：2003-08-29

    申请人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    发明人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1642

    摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

    摘要翻译： 计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。 该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。 主机/数据控制器还交织与多个存储器模块中的每一个相关联的多个通道上的数据。 为了优化存储器带宽并减少内存延迟，在本RAID系统中实现了各种技术。 现有技术包括提供双存储器仲裁器，通过芯片选择或库地址排序读取周期，提供可编程的上限和下限边界寄存器以便于可编程存储器映射，以及条带化和交织存储器数据以提供一个突发长度。

    Memory latency and bandwidth optimizations
    6.
    发明授权
    Memory latency and bandwidth optimizations 失效

    公开(公告)号：US06938133B2

    公开(公告)日：2005-08-30

    申请号：US09965913

    申请日：2001-09-28

    申请人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    发明人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    IPC分类号： G06F13/16 ,  G06F12/00

    CPC分类号： G06F13/1642

    摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). The host/data controller also interleaves data on a plurality of channels associated with each of the plurality of memory modules. To optimize memory bandwidth and reduce memory latency, various techniques are implemented in the present RAID system. Present techniques include providing dual memory arbiters, sorting read cycles by chip select or bank address, providing programmable upper and lower boundary registers to facilitate programmable memory mapping, and striping and interleaving memory data to provide a burst length of one.

    Memory auto-precharge
    7.
    发明授权
    Memory auto-precharge 有权
    内存自动预充电

    公开(公告)号：US06832286B2

    公开(公告)日：2004-12-14

    申请号：US10179081

    申请日：2002-06-25

    申请人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    发明人： Jerome J. Johnson ,  Benjamin H. Clark ,  Gary J. Piccirillo ,  John M. MacLaren

    IPC分类号： G06F1200

    CPC分类号： G06F13/4243

    摘要： A computer system includes a plurality of memory modules that contain semiconductor memory, such as DIMMs. The system includes a host/data controller that utilizes an XOR engine to store data and parity information in a striped fashion on the plurality of memory modules to create a redundant array of industry standard DIMMs (RAID). To optimally run back to back cycles to the memory modules, a technique for providing de-rating parameters such that unnecessary latencies designed into the memory devices can be removed while the system is executing requests. By removing any unnecessary latency, cycle time and overall system performance can be improved.

    摘要翻译： 计算机系统包括包含半导体存储器（诸如DIMM）的多个存储器模块。 该系统包括主机/数据控制器，其利用XOR引擎以条带方式在多个存储器模块上存储数据和奇偶校验信息，以创建工业标准DIMM（RAID）的冗余阵列。 为了最佳地运行到内存模块的反向循环，提供降级参数的技术，使得在系统执行请求时可以去除设计到存储器设备中的不必要的延迟。 通过消除任何不必要的延迟，可以提高周期时间和整体系统性能。