公开(公告)号：US08266411B2

公开(公告)日：2012-09-11

申请号：US12366169

申请日：2009-02-05

申请人： Tobias Gemmeke ,  Markus Kaltenbach ,  Nicolas Maeding

发明人： Tobias Gemmeke ,  Markus Kaltenbach ,  Nicolas Maeding

IPC分类号： G06F9/30

CPC分类号： G06F9/30076 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3861

摘要： Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.

摘要翻译： 改进的处理器代替具有包括固定架构操作数的指令集体系结构（ISA）的处理器，而不是用于计算指令（例如，乘法加载/存储指令）的附加特征位。 这些特定指令的附加位影响处理器对这些指令的处理。 另外，引入了新的指令来进一步使用所提出的方法。 通常，这些附加特征位以及指令可以由编译器自动生成，以为处理器提供相对适合的指令序列。

公开(公告)号：US20100199074A1

公开(公告)日：2010-08-05

申请号：US12366169

申请日：2009-02-05

申请人： Tobias Gemmeke ,  Markus Kaltenbach ,  Nicolas Maeding

发明人： Tobias Gemmeke ,  Markus Kaltenbach ,  Nicolas Maeding

IPC分类号： G06F9/30

CPC分类号： G06F9/30076 ,  G06F9/30185 ,  G06F9/30192 ,  G06F9/3832 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3861

摘要： Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.

摘要翻译： 改进的处理器代替具有包括固定架构操作数的指令集体系结构（ISA）的处理器，而不是用于计算指令（例如，乘法加载/存储指令）的附加特征位。 这些特定指令的附加位影响处理器对这些指令的处理。 此外，引入了新的指令以进一步使用所提出的方法。 通常，这些附加特征位以及指令可以由编译器自动生成，以为处理器提供相对适合的指令序列。

公开(公告)号：US09495490B2

公开(公告)日：2016-11-15

申请号：US13550207

申请日：2012-07-16

申请人： Christopher M Abernathy ,  Maarten J. Boersma ,  Markus Kaltenbach ,  Ulrike Schmidt

发明人： Christopher M Abernathy ,  Maarten J. Boersma ,  Markus Kaltenbach ,  Ulrike Schmidt

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F2217/78

摘要： A method detects active power dissipation in an integrated circuit. The method includes receiving a hardware design for the integrated circuit having one or more clock domains, wherein the hardware design comprises a local clock buffer for a clock domain, wherein the local clock buffer is configured to receive a clock signal and an actuation signal. The method includes adding instrumentation logic to the design for the clock domain, wherein the instrumentation logic is configured to compare a first value of the actuation signal determined at a beginning point of a test period to a second value of the actuation signal determined at a time when the clock domain is in an idle condition. The method includes detecting the clock domain includes unintended active power dissipation, in response to the first value of the actuation signal not being equal to the second value of the actuation signal.

摘要翻译： 一种方法可以检测集成电路中的有功功率。 该方法包括接收具有一个或多个时钟域的集成电路的硬件设计，其中硬件设计包括用于时钟域的本地时钟缓冲器，其中本地时钟缓冲器被配置为接收时钟信号和致动信号。 该方法包括将仪器逻辑添加到时钟域的设计中，其中仪器逻辑被配置为将在测试周期的起始点确定的致动信号的第一值与每次确定的致动信号的第二值进行比较 当时钟域处于空闲状态时。 响应于致动信号的第一值不等于致动信号的第二值，该方法包括检测时钟域包括非预期的有功功耗。

公开(公告)号：US09207995B2

公开(公告)日：2015-12-08

申请号：US13170003

申请日：2011-06-27

申请人： Maarten J. Boersma ,  Markus Kaltenbach ,  Jens Leenstra ,  Tim Niggemeier ,  Philipp Oehler ,  Philipp Panitz

发明人： Maarten J. Boersma ,  Markus Kaltenbach ,  Jens Leenstra ,  Tim Niggemeier ,  Philipp Oehler ,  Philipp Panitz

IPC分类号： G06F9/30 ,  G06F9/52 ,  G06F9/38

CPC分类号： G06F9/52 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/30189 ,  G06F9/3891

摘要： Various systems and processes may be used to speed up multi-threaded execution. In certain implementations, a system and process may include the ability to write results of a first group of execution units associated with a first register file into the first register file using a first write port of the first register file and write results of a second group of execution units associated with a second register file into the second register file using a first write port of the second register file. The system, apparatus, and process may also include the ability to connect, in a shared register file mode, results of the second group of execution units to a second write port of the first register file and connect, in a split register file mode, results of a part of the first group of execution units to the second write port of the first register file.

摘要翻译： 可以使用各种系统和过程来加速多线程执行。 在某些实现中，系统和过程可以包括使用第一寄存器堆的第一写入端口将与第一寄存器堆相关联的第一组执行单元的结果写入第一寄存器堆的能力，以及第二组的写入结果 使用第二寄存器文件的第一写入端口将与第二寄存器文件相关联的执行单元分配到第二寄存器堆中。 系统，装置和过程还可以包括以共享寄存器文件模式将第二组执行单元的结果连接到第一寄存器堆的第二写入端口并以分割寄存器文件模式连接的能力， 将第一组执行单元的一部分的结果提供给第一注册文件的第二写入端口。

公开(公告)号：US09164725B2

公开(公告)日：2015-10-20

申请号：US13181678

申请日：2011-07-13

申请人： Maarten J. Boersma ,  Markus Kaltenbach ,  Jens Leenstra ,  Tim Niggemeier ,  Philipp Oehler ,  Philipp Panitz

发明人： Maarten J. Boersma ,  Markus Kaltenbach ,  Jens Leenstra ,  Tim Niggemeier ,  Philipp Oehler ,  Philipp Panitz

IPC分类号： G06F7/00 ,  H04L9/32

CPC分类号： G06F7/00 ,  H04L9/3239 ,  H04L2209/125

摘要： Various systems, apparatuses, processes, and/or products may be used to calculate an SHA-2 hash function in a general-purpose processor. In some implementations, a system, apparatus, process, and/or product may include the ability to calculate at least one SHA-2 sigma function by using an execution unit adapted for performing a processor instruction, the execution unit including an integrated circuit primarily designed for calculating the SHA-2 sigma function(s), and calculating the SHA-2 hash function with general-purpose hardware processing components of the processor based on the sigma function(s). In certain implementations, the calculation of the SHA-2 sigma function(s) can be performed by the integrated circuit within a single instruction, allowing for a faster calculation of the SHA-2 hash function.

摘要翻译： 可以使用各种系统，装置，处理和/或产品来计算通用处理器中的SHA-2哈希函数。 在一些实现中，系统，装置，过程和/或产品可以包括通过使用适于执行处理器指令的执行单元来计算至少一个SHA-2σ功能的能力，所述执行单元包括主要设计的集成电路 用于计算SHA-2西格玛函数，以及基于σ函数计算具有处理器的通用硬件处理组件的SHA-2哈希函数。 在某些实现中，SHA-2西格玛函数的计算可以由单个指令中的集成电路执行，从而可以更快地计算SHA-2哈希函数。

公开(公告)号：US20150067298A1

公开(公告)日：2015-03-05

申请号：US14016607

申请日：2013-09-03

申请人： Maarten J. Boersma ,  Markus Kaltenbach ,  Christophe J. Layer ,  Silvia M. Mueller

发明人： Maarten J. Boersma ,  Markus Kaltenbach ,  Christophe J. Layer ,  Silvia M. Mueller

IPC分类号： G06F15/78

CPC分类号： G06F7/49936 ,  G06F7/00 ,  G06F7/483 ,  G06F7/49915 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30189 ,  G06F9/3887 ,  G06F15/78 ,  G06F15/8053 ,  G06F2207/382

摘要： A hardware circuit component configured to support vector operations in a scalar data path. The hardware circuit component configured to operate in a vector mode configuration and in a scalar mode configuration. The hardware circuit component configured to split the scalar mode configuration into a left half and a right half of the vector mode configuration. The hardware circuit component configured to perform one or more bit shifts over one or more stages of interconnected multiplexers in the vector mode configuration. The hardware circuit component configured to include duplicated coarse shift multiplexers at bit positions that receive data from both the left half and the right half of the vector mode configuration, resulting in one or more coarse shift multiplexers sharing the bit position.

摘要翻译： 配置为支持标量数据路径中的向量操作的硬件电路组件。 硬件电路组件被配置为以矢量模式配置和标量模式配置操作。 硬件电路组件被配置为将标量模式配置分解为向量模式配置的左半部分和右半部分。 硬件电路组件被配置为在矢量模式配置中的一个或多个互连多路复用器级上执行一个或多个位移位。 硬件电路组件被配置为在位向量模式配置的左半部分和右半部分接收数据的比特位置包括复制的粗略移位复用器，从而产生一个或多个共享比特位置的粗移位复用器。

公开(公告)号：US20130159666A1

公开(公告)日：2013-06-20

申请号：US13326249

申请日：2011-12-14

申请人： Maarten J. Boersma ,  Markus Kaltenbach ,  Christophe J. Layer ,  Jens Leenstra ,  Silvia M. Mueller

发明人： Maarten J. Boersma ,  Markus Kaltenbach ,  Christophe J. Layer ,  Jens Leenstra ,  Silvia M. Mueller

IPC分类号： G06F9/38 ,  G06F9/345 ,  G06F15/76 ,  G06F9/312

CPC分类号： G06F9/30036 ,  G06F9/345 ,  G06F9/38 ,  G06F9/3826 ,  G06F9/3867 ,  G06F9/3869 ,  G06F15/76 ,  G06F15/8053

摘要： Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.

摘要翻译： 描述了通过反转半抽头单指令多数据（SIMD）执行单元中的处理顺序来减少发出问题的延迟的技术。 在一个实施例中，提供了一种处理器功能单元，其包括前端单元和执行核心单元，后端单元，执行顺序控制信号单元，耦合在其中并且输出之间的第一互连和执行核心单元的输入以及耦合的第二互连 在后端单元的输出和前端单元的输入之间。 在操作中，执行顺序控制信号单元在接收到第一向量指令时基于所施加的时钟信号的奇偶校验产生转发顺序控制信号。 该控制信号又用于经由互连选择性地转发第一向量指令的执行结果的第一和第二部分，以用于依赖的第二向量指令的执行。

公开(公告)号：US20120150933A1

公开(公告)日：2012-06-14

申请号：US13183639

申请日：2011-07-15

申请人： Maarten J. Boersma ,  Markus Kaltenbach ,  Jens Leenstra ,  Tim Niggemeier ,  Philipp Oehler ,  Philipp Panitz

发明人： Maarten J. Boersma ,  Markus Kaltenbach ,  Jens Leenstra ,  Tim Niggemeier ,  Philipp Oehler ,  Philipp Panitz

IPC分类号： G06F7/52 ,  G06F7/50

CPC分类号： G06F7/53 ,  G06F2207/382 ,  G06F2207/3828

摘要： Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.

摘要翻译： 可以使用各种系统，装置，处理和程序来计算两个输入操作数的两次无进位乘法的乘法和。 在特定实施方案中，系统，装置，过程和程序可以包括使用用于输入操作数的输入数据总线和用于总体计算结果的输出数据总线的能力，每个总线包括2n位的宽度，其中n是 大于1的整数。 系统，装置，过程和程序还可以计算用于较低级别的分层结构的两个输入操作数的无进位乘法，并且计算用于更高级别的至少一个乘法和至少一个中间乘数和 基于较低级别的无进位乘法的结构级别。 可以根据所使用的全部宽度的输出数据总线，根据操作模式，输出一定数量的乘数作为总计算结果。

公开(公告)号：US20070283300A1

公开(公告)日：2007-12-06

申请号：US11740487

申请日：2007-04-26

申请人： Rolf Fritz ,  Markus Kaltenbach ,  Ulrich Mayer ,  Thomas Pflueger ,  Cordt Starke ,  Jan Van Lunteren

发明人： Rolf Fritz ,  Markus Kaltenbach ,  Ulrich Mayer ,  Thomas Pflueger ,  Cordt Starke ,  Jan Van Lunteren

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： The invention relates to a method and system for the design and implementation of state machine engines. A first constraints checking step checks a state transition function created by a designer against constraints imposed by the implementation technology in order to detect all portions of the state transition function that are in conflict with the constraints. A subsequent conflict resolution step tries to determine one or more suggested ways to meet the conflicting constraints, by investigating how the original state transition function can be modified such that all constraints are met. A final presentation and selection step provides the designer textual and/or graphically results of the constraints check and suggested modifications. The modifications can be accepted interactively, or the state transition function can be changed manually. In the latter case, the modified state transition function will be processed starting again with the constraints checking step.

摘要翻译： 本发明涉及一种用于设计和实施状态机发动机的方法和系统。 第一约束检查​​步骤检查由设计者创建的状态转换函数，以抵制由实施技术施加的约束，以便检测与约束相冲突的状态转换函数的所有部分。 随后的冲突解决步骤尝试通过调查如何修改原始状态转换功能以满足所有约束来确定满足冲突约束的一种或多种建议方式。 最后的演示和选择步骤为设计者提供了约束检查和建议修改的文本和/或图形结果。 可以交互接受修改，也可以手动更改状态转换功能。 在后一种情况下，将通过约束检查步骤再次开始处理修改的状态转换功能。

公开(公告)号：US08949575B2

公开(公告)日：2015-02-03

申请号：US13326249

申请日：2011-12-14

申请人： Maarten J. Boersma ,  Markus Kaltenbach ,  Christophe J. Layer ,  Jens Leenstra ,  Silvia M. Mueller

发明人： Maarten J. Boersma ,  Markus Kaltenbach ,  Christophe J. Layer ,  Jens Leenstra ,  Silvia M. Mueller

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F15/80

CPC分类号： G06F9/30036 ,  G06F9/345 ,  G06F9/38 ,  G06F9/3826 ,  G06F9/3867 ,  G06F9/3869 ,  G06F15/76 ,  G06F15/8053

摘要： Techniques for reducing issue-to-issue latency by reversing processing order in half-pumped single instruction multiple data (SIMD) execution units are described. In one embodiment a processor functional unit is provided comprising a frontend unit, and execution core unit, a backend unit, an execution order control signal unit, a first interconnect coupled between and output and an input of the execution core unit and a second interconnect coupled between an output of the backend unit and an input of the frontend unit. In operation, the execution order control signal unit generates a forwarding order control signal based on the parity of an applied clock signal on reception of a first vector instruction. This control signal is in turn used to selectively forward first and second portions of an execution result of the first vector instruction via the interconnects for use in the execution of a dependent second vector instruction.