公开(公告)号：US20240047210A1

公开(公告)日：2024-02-08

申请号：US17879873

申请日：2022-08-03

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Christopher Cole ,  Steven Grzeskowiak ,  Katie Lutker-Lee ,  Xinghua Sun ,  Daniel Santos Rivera

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0332 ,  H01L21/31144

Abstract: A method of processing a substrate that includes: forming recesses in a first mask layer over a mask stack including a lower hardmask, a middle mask, and an upper hardmask, the recesses defining an initial pattern including a plurality of spacer structures, each of the spacer structures having a first sidewall and an opposite second sidewall, the first sidewall having a different height from the second sidewall; etching the upper hardmask, selectively to the middle mask, to transfer the initial pattern to the upper hardmask; etching the middle mask, selectively to the lower hardmask and the patterned upper hardmask, to transfer a pattern of the patterned upper hardmask to the middle mask; and etching the lower hardmask, selectively to the patterned middle mask, to transfer a pattern of the patterned middle mask to the lower hardmask.

公开(公告)号：US11658038B2

公开(公告)日：2023-05-23

申请号：US17317587

申请日：2021-05-11

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Christopher Cole ,  Qiaowei Lou

IPC: H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31116 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/31138

Abstract: A substrate processing method is described for etching silicon carbide films for resist underlayer applications. The method includes providing a substrate containing a silicon carbide film thereon, and a photoresist layer defining a pattern over the silicon carbide film, plasma-exciting an etching gas containing a fluorocarbon-containing gas and an oxygen-containing gas, and exposing the substrate to the plasma-excited etching gas to transfer the pattern to the silicon carbide film, where at least a portion of a thickness of the photoresist layer survives the exposing. For example, the photoresist layer includes an EUV resist layer and the etching gas includes C4F8 gas, O2 gas, and Ar gas. In another example, the exposing includes exposing the substrate to a) a plasma-excited etching gas containing C4F8 gas, O2 gas, and Ar gas, and b) exposing the substrate to a plasma-excited Ar gas, where steps a) and b) are sequentially performed at least once.

公开(公告)号：US20210358763A1

公开(公告)日：2021-11-18

申请号：US17317587

申请日：2021-05-11

Applicant: Tokyo Electron Limited

Inventor： Angelique Raley ,  Christopher Cole ,  Qiaowei Lou

IPC: H01L21/311 ,  H01L21/033

Abstract: A substrate processing method is described for etching silicon carbide films for resist underlayer applications. The method includes providing a substrate containing a silicon carbide film thereon, and a photoresist layer defining a pattern over the silicon carbide film, plasma-exciting an etching gas containing a fluorocarbon-containing gas and an oxygen-containing gas, and exposing the substrate to the plasma-excited etching gas to transfer the pattern to the silicon carbide film, where at least a portion of a thickness of the photoresist layer survives the exposing. For example, the photoresist layer includes an EUV resist layer and the etching gas includes C4F8 gas, O2 gas, and Ar gas. In another example, the exposing includes exposing the substrate to a) a plasma-excited etching gas containing C4F8 gas, O2 gas, and Ar gas, and b) exposing the substrate to a plasma-excited Ar gas, where steps a) and b) are sequentially performed at least once.

公开(公告)号：US10854453B2

公开(公告)日：2020-12-01

申请号：US16005614

申请日：2018-06-11

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Christopher Cole ,  Andrew W. Metz

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02

Abstract: A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.

公开(公告)号：US20180358227A1

公开(公告)日：2018-12-13

申请号：US16005614

申请日：2018-06-11

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Christopher Cole ,  Andrew W. Metz

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/0338 ,  H01L21/02118 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

Abstract: A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.