公开(公告)号：US11456185B2

公开(公告)日：2022-09-27

申请号：US16896655

申请日：2020-06-09

Applicant: Tokyo Electron Limited

Inventor： Ryan Burns ,  Mark Somervell ,  Corey Lemley

IPC: H01L21/321 ,  H01L21/467 ,  H01L21/02

Abstract: In certain embodiments, a method for processing a substrate includes applying a surface treatment to selected surfaces of the substrate. The substrate has a non-planar topography including structures defining recesses. The method further includes depositing a fill material on the substrate by spin-on deposition. The surface treatment directs the fill material to the recesses and away from the selected surfaces to fill the recesses with the fill material without adhering to the selected surfaces. The method further includes removing the surface treatment from the selected surfaces of the substrate and depositing a planarizing film on the substrate by spin-on deposition. The planarizing film is deposited on the selected surfaces and top surfaces of the fill material.

公开(公告)号：US20210303741A1

公开(公告)日：2021-09-30

申请号：US16829416

申请日：2020-03-25

Applicant: Tokyo Electron Limited

Inventor： Ryan Burns ,  Mark Somervell

IPC: G06F30/10

Abstract: Methods used to more accurately predict spin on layer planarization over a patterned topography are provided. Methods are provided for generating a layer critical dimension model. In one embodiment, the critical dimension model is a layer thickness model that more accurately simulates patterned topography trends, as a function of feature dimensions, surrounding pattern density and radial position across the patterned topography. Additional methods are provided for calibrating the layer thickness model over one or more spatial areas to account for radial variations in the patterned topography. Further methods are provided for using one or more calibrated layer thickness models to predict a thickness of a layer (e.g., a spin on coating) as it is being deposited onto a patterned substrate. The methods disclosed herein may facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar layer or layer on the substrate.

公开(公告)号：US11455436B2

公开(公告)日：2022-09-27

申请号：US16829416

申请日：2020-03-25

Applicant: Tokyo Electron Limited

Inventor： Ryan Burns ,  Mark Somervell

IPC: G06F30/10 ,  G06F119/18 ,  G03F7/16

Abstract: Methods used to more accurately predict spin on layer planarization over a patterned topography are provided. Methods are provided for generating a layer critical dimension model. In one embodiment, the critical dimension model is a layer thickness model that more accurately simulates patterned topography trends, as a function of feature dimensions, surrounding pattern density and radial position across the patterned topography. Additional methods are provided for calibrating the layer thickness model over one or more spatial areas to account for radial variations in the patterned topography. Further methods are provided for using one or more calibrated layer thickness models to predict a thickness of a layer (e.g., a spin on coating) as it is being deposited onto a patterned substrate. The methods disclosed herein may facilitate the planarization (i.e., flatness) of spin-on coatings during the device fabrication to form a uniformly planar layer or layer on the substrate.

公开(公告)号：US11262657B2

公开(公告)日：2022-03-01

申请号：US16511211

申请日：2019-07-15

Applicant: Tokyo Electron Limited

Inventor： Michael Carcasi ,  Ryan Burns ,  Mark Somervell

IPC: G03F7/09 ,  G03F7/38 ,  G03F7/16 ,  G03F7/20 ,  G03F7/30

Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin coatings of a substrate. More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

公开(公告)号：US20210018839A1

公开(公告)日：2021-01-21

申请号：US16511211

申请日：2019-07-15

Applicant: Tokyo Electron Limited

Inventor： Michael Carcasi ,  Ryan Burns ,  Mark Somervell

IPC: G03F7/09 ,  G03F7/38 ,  G03F7/30 ,  G03F7/16 ,  G03F7/20

Abstract: Described herein are technologies to facilitate device fabrication, especially those that involve spin coatings of a substrate. More particularly, technologies described herein facilitate the planarization (i.e., flatness) of spin coatings during the device fabrication to form a uniformly planar film or layer on the substrate. This abstract itself is not intended to limit the scope of this patent. The scope of the present invention is pointed out in the appending claims.

公开(公告)号：US20250105066A1

公开(公告)日：2025-03-27

申请号：US18373582

申请日：2023-09-27

Applicant: Tokyo Electron Limited

Inventor： Sean Berglund ,  Michael Carcasi ,  Robert Brandt ,  Joshua Hooge ,  Ankur Agarwal ,  Ryan Burns

IPC: H01L21/66 ,  G03F7/00 ,  G03F7/004 ,  H01L21/67

Abstract: Various embodiments of improved systems and methods are provided herein to monitor process chemicals used in a semiconductor process. More specifically, new semiconductor processing systems and methods that utilize infrared (IR) spectroscopy techniques are provided herein to monitor the composition and/or concentration of process chemicals utilized to process a substrate and/or the by-products produced during substrate processing. By monitoring the process chemicals and/or the by-products in real-time, the systems and methods described herein can be used to provide better process control and/or end-point detection for a wide variety of semiconductor processes.

公开(公告)号：US20230259030A1

公开(公告)日：2023-08-17

申请号：US17887946

申请日：2022-08-15

Applicant: Tokyo Electron Limited

Inventor： Michael Carcasi ,  Ryan Burns ,  Lior Huli

IPC: G03F7/11 ,  H01L21/027 ,  G03F7/16 ,  G03F7/38 ,  G03F7/004

CPC classification number: G03F7/11 ,  H01L21/0274 ,  G03F7/162 ,  G03F7/38 ,  G03F7/0043

Abstract: In certain embodiments, a method of microfabrication includes forming a layer stack on a wafer, the layer stack including a photoresist layer formed on an underlying layer. The method further includes depositing a barrier layer on the photoresist layer, the barrier layer selected to prevent penetration from one or more environmental components. The method further includes exposing the photoresist layer to a pattern of actinic radiation and developing the photoresist layer.