Electronic device and timer therefor with tamper event time stamp features and related methods
    1.
    发明授权
    Electronic device and timer therefor with tamper event time stamp features and related methods 有权
    电子设备和定时器,具有篡改事件时间戳功能和相关方法

    公开(公告)号:US07844837B2

    公开(公告)日:2010-11-30

    申请号:US11854816

    申请日:2007-09-13

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: G01R21/133 G01R22/066

    Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

    Abstract translation: 电子计时器可以包括时钟参考信号发生器和用于基于时钟参考信号产生实时数据的实时时钟(RTC)电路。 RTC电路可以包括多个寄存器,每个寄存器用于存储实时数据的相应位。 此外,每个寄存器可以包括用于初始存储实时数据位的主锁存器,用于随后存储实时数据位的从锁存器和用于从从锁存器存储实时数据位的用户锁存器。 RTC电路还可以包括用于使得至少一些寄存器基于时钟参考信号而增加的控制器。 此外,电子计时器还可以有利地包括用于接收篡改事件信号的篡改电路,并使每个用户锁存器在其中保持时间戳。

    Method and apparatus for increasing comparator gain without affecting
standby current
    2.
    发明授权
    Method and apparatus for increasing comparator gain without affecting standby current 有权
    提高比较器增益而不影响待机电流的方法和装置

    公开(公告)号:US06084390A

    公开(公告)日:2000-07-04

    申请号:US217323

    申请日:1998-12-21

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: H02J9/061 G05F3/242 Y10T307/625

    Abstract: A power supply switching circuit ensures stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal, also derived from the primary voltage but having a different rate of change than the first voltage signal, to generate a compare output signal. The first and second voltage signals are characterized as being equal to each other when the primary voltage is equal to a predetermined crossover point at which the integrated circuit device will be powered by the primary voltage. When the primary voltage is less than the predetermined crossover point, a transistor element of a reference leg of a current mirror of the power supply switching circuit operates in back-bias mode and is sized large enough to ensure that the reference leg generates a large enough current to stabilize operation of the comparison element as the primary voltage ramps up until the primary voltage exceeds the predetermined crossover point.

    Abstract translation: 电源开关电路确保集成电路的主电源和次电源之间的稳定,及时且准确的转换。 电路的比较元件将源自主电源的初级电压的第一电压信号与也从第一电压得到但具有与第一电压信号不同的变化率的第二电压信号进行比较,以产生比较 输出信号。 第一和第二电压信号的特征在于当初级电压等于集成电路器件将被初级电压供电的预定的交叉点时彼此相等。 当初级电压小于预定的交叉点时,电源开关电路的电流镜的参考支路的晶体管元件以反偏压模式工作,并且其尺寸足够大以确保参考支脚产生足够大的 当初级电压升高直到初级电压超过预定的交叉点时,比较元件的电流稳定稳定。

    Electronic device and timer therefor with tamper event stamp features and related methods
    3.
    发明授权
    Electronic device and timer therefor with tamper event stamp features and related methods 有权
    电子设备和定时器,具有篡改事件时间戳功能和相关方法

    公开(公告)号:US07287169B2

    公开(公告)日:2007-10-23

    申请号:US10268871

    申请日:2002-10-10

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: G01R21/133 G01R22/066

    Abstract: An electronic timer may include a clock reference signal generator and a real time clock (RTC) circuit for generating real time data based upon the clock reference signal. The RTC circuit may include a plurality of registers each for storing a respective bit of the real time data. Further, each register may include a master latch for initially storing the real time data bit, a slave latch for subsequently storing the real time data bit, and a user latch for storing the real time data bit from the slave latch. The RTC circuit may further include a controller for causing at least some of the registers to increment based upon the clock reference signal. Additionally, the electronic timer may also advantageously include a tamper circuit for receiving a tamper event signal and causing each of the user latches to hold a time stamp therein.

    Abstract translation: 电子计时器可以包括时钟参考信号发生器和用于基于时钟参考信号产生实时数据的实时时钟(RTC)电路。 RTC电路可以包括多个寄存器,每个寄存器用于存储实时数据的相应位。 此外,每个寄存器可以包括用于初始存储实时数据位的主锁存器,用于随后存储实时数据位的从锁存器和用于从从锁存器存储实时数据位的用户锁存器。 RTC电路还可以包括用于使得至少一些寄存器基于时钟参考信号而增加的控制器。 此外,电子计时器还可以有利地包括用于接收篡改事件信号的篡改电路,并使每个用户锁存器在其中保持时间戳。

    Method and structure for measurement of a multiple-power-source device during a test mode
    4.
    发明授权
    Method and structure for measurement of a multiple-power-source device during a test mode 有权
    在测试模式下测量多电源设备的方法和结构

    公开(公告)号:US06365991B1

    公开(公告)日:2002-04-02

    申请号:US09450108

    申请日:1999-11-29

    Abstract: A test mode structure and method of a multi-power-source device provides for the device to remain in a test mode, during which current draw of the device may be accurately measured, even after primary power supply to the device has been greatly reduced or completely removed. Significant reduction or removal of the primary power supply while still remaining in the test mode is necessary to counter the presence of a variable current that would otherwise be normally generated by the multi-power-source device in the test mode; the presence of the variable current during the test mode, if not negated, will not permit an accurate measurement of the current draw of the multi-power-source device. Significant reduction or removal of the primary power supply to the device would typically cause the multi-power-source device to exit the test mode and switch to a secondary supply voltage supplied by the secondary power supply, thereby foiling any attempt to measure the current draw of the device. An external control signal provided to the device ensures that the test mode remains enabled, thereby inhibiting the device from exiting the test mode and switching to the secondary power supply in a normal operating mode.

    Abstract translation: 多功率源装置的测试模式结构和方法提供了设备保持在测试模式中,即使在设备的主要电力供应已被大大降低之后,也可准确地测量设备的电流消耗, 完全删除 在仍然保持在测试模式中时,主电源的显着减少或去除对于在测试模式中存在否则通常由多电源​​设备产生的可变电流是必要的; 在测试模式期间存在可变电流(如果不被否定)将不能准确地测量多电源装置的电流消耗。 显着减少或移除设备的主电源通常将导致多电源设备退出测试模式并切换到次级电源提供的次级电源电压,从而防止任何测量电流消耗的尝试 的设备。 提供给设备的外部控制信号确保测试模式保持启用,从而禁止设备退出测试模式,并在正常操作模式下切换到次级电源。

    DIGITAL INPUT BUFFER
    5.
    发明申请
    DIGITAL INPUT BUFFER 审中-公开
    数字输入缓冲器

    公开(公告)号:US20130063195A1

    公开(公告)日:2013-03-14

    申请号:US13467256

    申请日:2012-05-09

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: H03K3/356104

    Abstract: A digital input buffer and method. The input buffer includes a voltage regulator configured for operating in weak inversion and outputting a regulated potential, an inverter having as its power source the regulated potential and configured for receiving an input signal, a first latch having its input coupled to the inverter input, and a second latch having its input coupled to the inverter's output, having its output coupled to the first latch's enable input, and having its enable input coupled to the first latch's output. A first latch output signal from the first latch output and a second latch output signal from the second latch output enable switching the first latch output signal to the complement of the input signal and switching the second latch output signal to that of the input signal.

    Abstract translation: 数字输入缓冲器和方法。 所述输入缓冲器包括被配置为在弱反相中操作并输出调节电位的电压调节器,具有作为其电源的调节电位并被配置为接收输入信号的反相器,具有耦合到所述逆变器输入的其输入的第一锁存器,以及 第二锁存器,其输入端耦合到反相器的输出,其输出端耦合到第一锁存器的使能输入,并且其使能输入耦合到第一锁存器的输出端。 来自第一锁存器输出的第一锁存器输出信号和来自第二锁存器输出的第二锁存器输出信号使得能够将第一锁存器输出信号切换到输入信号的补码,并将第二锁存器输出信号切换到输入信号的补码。

    Circuit and method for detecting the state of a switch with reduced power
    6.
    发明授权
    Circuit and method for detecting the state of a switch with reduced power 有权
    用于检测具有降低功率的开关状态的电路和方法

    公开(公告)号:US06909313B2

    公开(公告)日:2005-06-21

    申请号:US10147639

    申请日:2002-05-17

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: H01H9/167 H03K17/18 Y10T307/74 Y10T307/766

    Abstract: A circuit and method are disclosed for detecting activation of a switch, such as a mechanical switch, having a first terminal coupled to two or more voltage sources, with each voltage source providing a distinct voltage level representing a logic high level. The circuit includes first circuitry, having an output coupled to the switch for initially placing a first voltage across the switch representative of a logic low level. The circuit further includes second circuitry having an input coupled to the switch for sensing a voltage differential appearing across the switch and an output for indicating whether the voltage appearing across the switch is at any voltage representative of the logic high level, the second circuitry being controlled to selectively eliminate static current drawn by the circuit based upon the value of the output of the second circuitry.

    Abstract translation: 公开了用于检测诸如机械开关的开关的电路和方法,其具有耦合到两个或更多个电压源的第一端子,每个电压源提供表示逻辑高电平的不同电压电平。 该电路包括第一电路,其具有耦合到开关的输出,用于初始地在表示逻辑低电平的开关上放置第一电压。 电路还包括具有耦合到开关的输入的第二电路,用于感测跨越开关出现的电压差异,以及用于指示出现在开关两端的电压是否处于代表逻辑高电平的任何电压的输出,第二电路被控制 以基于第二电路的输出值来选择性地消除由电路吸取的静电流。

    Apparatus and method for switching between two power supplies of an
integrated circuit
    7.
    发明授权
    Apparatus and method for switching between two power supplies of an integrated circuit 有权
    用于在集成电路的两个电源之间切换的装置和方法

    公开(公告)号:US6118188A

    公开(公告)日:2000-09-12

    申请号:US217321

    申请日:1998-12-21

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: H03K3/02337 H03K17/693 H03K3/02335 Y10T307/50

    Abstract: A power supply switching circuit employs hysteresis to ensure stable, timely, and accurate transition between a primary power source and a secondary power source of an integrated circuit. A comparison element of the circuit compares a first voltage signal derived from a primary voltage of the primary power source to a second voltage signal provided by the secondary power source in order to generate a compare output signal. A voltage divider element of the circuit, characterized as having a RC constant, is coupled to the primary power source and receives the compare signal generated by the comparison element and generates the first voltage signal. A bypass element of the circuit is coupled to the voltage divider element and is controlled by the compare signal to bypass the RC constant of the voltage divider element by immediately pulling the first voltage signal to the primary voltage when, after powering up the primary power source, the first voltage signal becomes greater than the second voltage signal.

    Abstract translation: 电源开关电路使用滞后来确保集成电路的主电源和次电源之间的稳定,及时,准确的转换。 电路的比较元件将从主电源的初级电压导出的第一电压信号与由次级电源提供的第二电压信号进行比较,以便产生比较输出信号。 电路的分压器元件,其特征在于具有RC常数,耦合到主电源并接收由比较元件产生的比较信号并产生第一电压信号。 电路的旁路元件耦合到分压器元件,并且由比较信号控制以绕过分压器元件的RC常数,通过在将主电源上电之后立即将第一电压信号拉至初级电压 ,第一电压信号变得大于第二电压信号。

    Power on reset circuit
    8.
    发明申请

    公开(公告)号:US20060091920A1

    公开(公告)日:2006-05-04

    申请号:US10978852

    申请日:2004-11-01

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: H03K3/356008 H03K17/223

    Abstract: A power on reset circuit includes a pulse generation circuit that is connected to receive a supply voltage and respond to an initial ramp-up of that supply voltage to generate an output pulse that transitions from a low to a relatively high state tracking the supply voltage ramp-up. The pulse generation circuit further sets a feedback node in an enable state. Responsive to a flip signal received at an input node, the pulse generation circuit then transitions the output pulse from the relatively high state to the low state and sets the feedback node in a disable state. A static current control transistor switch includes a source-drain circuit coupled to the supply voltage and further includes a gate. The gate is connected to the feedback node such that the transistor switch is actuated in response to the feedback node enable state and unactuated in response to the feedback node disable state. A resistive divider circuit, including at least two resistors connected in series with each other at a tap, is connected in series with the source-drain circuit of the static current control transistor. The tap of the resistive divides circuit is connected to the input node of the pulse generation circuit to supply the flip signal.

    Method and circuit for detecting the state of a switch
    9.
    发明授权
    Method and circuit for detecting the state of a switch 有权
    用于检测开关状态的方法和电路

    公开(公告)号:US06861955B2

    公开(公告)日:2005-03-01

    申请号:US10404885

    申请日:2003-03-31

    Applicant: Tom Youssef

    Inventor: Tom Youssef

    CPC classification number: H03K17/18 G01R31/31721 G08B13/02 H01H9/167

    Abstract: A circuit for detecting the state of a switch having a first circuit which substantially periodically attempts to provide a voltage across the switch. A second circuit detects the state of the switch by monitoring the voltage across the switch, and responsively generates an output having a voltage level representative of the voltage appearing across the switch.

    Abstract translation: 用于检测具有第一电路的开关的状态的电路,其基本上周期性地尝试在开关上提供电压。 第二电路通过监视开关两端的电压来检测开关的状态,并且响应地产生具有代表开关两端出现的电压的电压电平的输出。

    Method and circuit for switchover between a primary and a secondary power source
    10.
    发明授权
    Method and circuit for switchover between a primary and a secondary power source 有权
    主电源和次电源之间切换的方法和电路

    公开(公告)号:US06787938B1

    公开(公告)日:2004-09-07

    申请号:US09626550

    申请日:2000-07-27

    CPC classification number: G11C5/141 Y10T307/615 Y10T307/625 Y10T307/826

    Abstract: An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

    Abstract translation: 一种用于提供从主电源到次电源的切换以防止易失性元件丢失存储的数据的集成电路和方法。 集成电路包括强制电源切换电路,用于检测主电源的电源电平低于预定阈值电平。 集成电路中的切换电路基于强制电源切换电路检测到从主电源接收的电源电平下降到低于预定阈值水平的情况下开始切换操作。 强制电源切换电路的检测可能发生在比预定的负变化率更快地转变的信号电平上。 集成电路可以并入具有诸如存储器或时钟之类的易失性元件的任何系统中。

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