摘要:
An integrated burst FSK receiver is provided to receive and interpret an RF signal using FSK modulation. The integrated burst FSK receiver uses a programmable RF local oscillator to mix a received signal down to an IF range or baseband, where it is filtered and sampled for subsequent digital processing. Digital filtering and detection are employed to improve overall bit error rate performance and receiver sensitivity. A programmable digital low-pass or band-pass filter can also be used to suppress interference. A matched filter correlator can be used for detection and symbol timing adjustment in one mode, while an adaptive frequency comparator can be used in another mode. Circuits are provided that estimate carrier offset, frequency deviation and signal strength. These measurements can then be used to optimize the receiver performance. A method for receiving and interpreting an RF signal using FSK modulation is also provided.
摘要:
An integrated burst FSK receiver is provided to receive and interpret an RF signal using FSK modulation. The integrated burst FSK receiver uses a programmable RF local oscillator to mix a received signal down to an IF range or baseband, where it is filtered and sampled for subsequent digital processing. Digital filtering and detection are employed to improve overall bit error rate performance and receiver sensitivity. A programmable digital low-pass or band-pass filter can also be used to suppress interference. A matched filter correlator can be used for detection and symbol timing adjustment in one mode, while an adaptive frequency comparator can be used in another mode. Circuits are provided that estimate carrier offset, frequency deviation and signal strength. These measurements can then be used to optimize the receiver performance. A method for receiving and interpreting an RF signal using FSK modulation is also provided.
摘要:
In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified. If the maximum value exceeds a threshold, it will be declared as a peak and the address associated is the peak timing.
摘要:
In an integrated satellite receiver, improved header acquisition techniques are described for quickly locating a header symbol sequence in a data stream substantially implemented on a single CMOS integrated circuit. To identify the location of a header symbol sequence in a data stream, a selected header acquisition technique employs a real time correlator followed by an accumulator. In accordance with an alternative embodiment which reduces the cost very efficiently, a real time correlator is followed by a comparator to pick out and store the top N correlator values from NS symbols in a frame. The timing addresses associated with the stored correlator values are used during an accumulation mode of operation whereby a cumulative memory is used to accumulate the correlator value of each stored timing address. Once accumulation over a predetermined number of frames is finished, the largest or maximum value among the accumulated correlator values is identified. If the maximum value exceeds a threshold, it will be declared as a peak and the address associated is the peak timing.
摘要:
Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.
摘要:
Quadrature receiver sampling architecture. A signal ADC performs analog to digital conversion for both I and Q streams. An analog MUX selects the appropriate I and the Q baseband analog input streams for input to the ADC at the appropriate time. A digital filter may also be employed to compensate for any introduced delay between the samples of the I and Q channel when seeking to recover the symbols that have been transmitted to a communication receiver that employs this quadrature receiver architecture and/or signal processing. In one embodiment, if an ADC is clocked at a rate of substantially twice the sample rate of the I and Q channels, there will be a one-half sample clock delay between the digital I and digital Q data at the output of the ADC. This delay is then removed before the demodulator processes the input signals to recover the transmitted symbols.
摘要:
Sample rate reduction in data communication receivers. Digital sampling of analog data is performed using a reduced sample rate. The reduction factor may be any number of factors including a factor that divides the sample rate by a factor of two. The reduction of the sampling frequency is from a sampling frequency that is greater than twice the highest frequency component in an analog input signal. These analog input signals may be I and Q streams in certain embodiments. A digital interpolation filter may be employed to increase (up-convert) the sample rate of a digital signal before it is input to a VID filter that is used to recover the transmitted symbols from the over-sampled data stream. In this embodiment, this technique allows a front end of a communication receiver to be clocked at a lower sampling rate without affecting the performance of the VID filter.
摘要:
Systems and methods for performing phase tracking scheme for an Analog to Digital converter based tuner. In many embodiments, a phase tracking scheme is used that includes a phase locked loop that corrects the phase of the output signals and an amplitude modulation compensator that modulates the amplitude of the output digital signals to compensate for phase noise based upon the received output digital signals.
摘要:
A frequency translation module for a broadband multi-channel communication system may include an analog signal converter, a digital channel selection device, and a digital-to-analog (D/A) converter. The analog signal converter is configured to receive a plurality of analog signals, to select analog signals residing in a predefined frequency band, and to convert each of the selected analog signals into a digital signal. The digital channel selection device is configured to process digital signals corresponding to the selected analog signals and to generate a composite output of digital signals representative of the selected analog signals. The D/A converter is configured to translate the composite output to an analog signal output decodable by a receiver. Further, the frequency translation module may include a mixer configured to upconvert the analog signal output to a frequency decodable by the receiver.
摘要翻译:用于宽带多通道通信系统的频率转换模块可以包括模拟信号转换器,数字通道选择装置和数模(D / A)转换器。 模拟信号转换器被配置为接收多个模拟信号,以选择驻留在预定频带中的模拟信号,并将所选择的模拟信号中的每一个转换为数字信号。 数字通道选择装置被配置为处理对应于所选择的模拟信号的数字信号,并产生表示所选模拟信号的数字信号的复合输出。 D / A转换器被配置为将复合输出转换成可由接收器解码的模拟信号输出。 此外,频率转换模块可以包括配置成将模拟信号输出上变频到由接收机解码的频率的混频器。
摘要:
Certain aspects of a method and system for satellite communication are disclosed. Aspects of one method may include a receiver that handles digital video broadcasting. The receiver may be enabled to dynamically vary spacing between one or more pilots within at least one frame based on a determined symbol rate. The size of each of a plurality of received programs may be determined and the spacing between one or more pilots may be dynamically varied based on the determined size of each of the plurality of received programs.