公开(公告)号：US09143436B2

公开(公告)日：2015-09-22

申请号：US13359635

申请日：2012-01-27

申请人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

发明人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

IPC分类号： H04L12/801 ,  H04L12/729 ,  H04L12/727 ,  H04L12/721 ,  H04L12/26

CPC分类号： H04L45/125 ,  H04L43/0882 ,  H04L45/121 ,  H04L45/127 ,  H04L45/70 ,  H04L47/115

摘要： An information processing apparatus connected to another information apparatus in a parallel computer system via a plurality of routes, includes: an arithmetic processing device to issue an instruction for collection of congestion information and for communication; a route information holding unit to hold route information for performing communication; a transmission unit to transmit a congestion information collection packet to any of the plurality of routes; a reception unit to receive a congestion information collection response packet corresponding to the congestion information collection packet from any of the plurality of routes; and a control unit to cause the transmission unit to transmit a congestion information collection packet, to select route information from the route information holding unit based on congestion information included in the congestion information collection response packet, and to cause the transmission unit to perform communication instructed by the arithmetic processing device based on the selected route information.

摘要翻译： 一种信息处理装置，其通过多条路径与并行计算机系统中的另一信息装置连接，包括：发出用于收集拥塞信息和通信的指令的运算处理装置; 路由信息保持单元，保存用于进行通信的路由信息​​; 发送单元，向所述多个路由中的任一个发送拥塞信息收集分组; 接收单元，用于从所述多个路由中的任一个接收与所述拥塞信息收集分组相对应的拥塞信息收集响应分组; 以及控制单元，用于使所述发送单元发送拥塞信息收集包，基于所述拥挤信息收集响应包中包含的拥塞信息，从所述路径信息保持单元选择路由信息，并使所述发送单元进行通信指示 由算术处理装置基于所选择的路线信息。

公开(公告)号：US08504731B2

公开(公告)日：2013-08-06

申请号：US12942291

申请日：2010-11-09

申请人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

发明人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

IPC分类号： G06F15/16

CPC分类号： G06F15/16 ,  G06F15/17337

摘要： In a parallel computer system including a plurality of processors, processors are classified into a plurality of groups including a prescribed number of processors, and processors are connected to each other in a complete connecting manner in the groups. Those groups are connected to each other as the respective processors are connected in linear to each other.

摘要翻译： 在包括多个处理器的并行计算机系统中，将处理器分为包括规定数量的处理器的多个组，并且处理器以组中的完全连接方式彼此连接。 当各个处理器彼此线性连接时，这些组彼此连接。

公开(公告)号：US08204054B2

公开(公告)日：2012-06-19

申请号：US12706137

申请日：2010-02-16

申请人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

发明人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

IPC分类号： H04L12/56

CPC分类号： G06F15/17368

摘要： A system has a plurality of nodes connected in a multi-dimensional matrix and having node addresses, respectively, each of the nodes having a processor, and a router for transmitting a request packet to a node adjacent to its own node located in n+1th dimension when the address of nth dimension of its own node is matched to the address of nth dimension of the target node, transmitting a response packet to a node adjacent to its own node located in nth dimension when the address of n+1th dimension of its own node is matched to the address of n+1th dimension of the response packet, wherein the router terminates a request packet when the address of the request packet is fully matched to the node address of its own node in all the dimensions, transfers the data conveyed by the request packet to the processor of its own node for processing.

摘要翻译： 一种系统具有以多维矩阵连接并具有节点地址的多个节点，每个节点具有处理器，以及路由器，用于将请求分组发送到与其位于第n + 1个的其自身节点相邻的节点 当其自身节点的第n维的地址与目标节点的第n维的地址匹配时，将其响应分组发送到邻近于其位于第n维的其自身节点的节点，当其第n维的第n维的地址 自身节点与响应分组的n + 1维的地址相匹配，其中当请求分组的地址在所有维度上与其自身节点的节点地址完全匹配时，路由器终止请求分组，传送数据 由请求包传送到其自身节点的处理器进行处理。

公开(公告)号：US09619300B2

公开(公告)日：2017-04-11

申请号：US13166114

申请日：2011-06-22

申请人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

发明人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

IPC分类号： G06F9/52 ,  G06F9/30

CPC分类号： G06F9/522 ,  G06F9/30

摘要： A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation and executes the reduction operation. The synchronization unit in the reduction operation device detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of the arithmetic unit.

公开(公告)号：US20120250514A1

公开(公告)日：2012-10-04

申请号：US13359635

申请日：2012-01-27

申请人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

发明人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

IPC分类号： H04L12/24

CPC分类号： H04L45/125 ,  H04L43/0882 ,  H04L45/121 ,  H04L45/127 ,  H04L45/70 ,  H04L47/115

摘要： An information processing apparatus connected to another information apparatus in a parallel computer system via a plurality of routes, includes: an arithmetic processing device to issue an instruction for collection of congestion information and for communication; a route information holding unit to hold route information for performing communication; a transmission unit to transmit a congestion information collection packet to any of the plurality of routes; a reception unit to receive a congestion information collection response packet corresponding to the congestion information collection packet from any of the plurality of routes; and a control unit to cause the transmission unit to transmit a congestion information collection packet, to select route information from the route information holding unit based on congestion information included in the congestion information collection response packet, and to cause the transmission unit to perform communication instructed by the arithmetic processing device based on the selected route information.

摘要翻译： 一种信息处理装置，其通过多条路径与并行计算机系统中的另一信息装置连接，包括：发出用于收集拥塞信息和通信的指令的运算处理装置; 路由信息保持单元，保存用于进行通信的路由信息​​; 发送单元，向所述多个路由中的任一个发送拥塞信息收集分组; 接收单元，用于从所述多个路由中的任一个接收与所述拥塞信息收集分组相对应的拥塞信息收集响应分组; 以及控制单元，用于使所述发送单元发送拥塞信息收集包，基于所述拥挤信息收集响应包中包含的拥塞信息，从所述路径信息保持单元选择路由信息，并使所述发送单元进行通信指示 由算术处理装置基于所选择的路线信息。

公开(公告)号：US20120159121A1

公开(公告)日：2012-06-21

申请号：US13323936

申请日：2011-12-13

申请人： Tomohiro INOUE ,  Yuichiro Ajima ,  Shinya Hiramoto

发明人： Tomohiro INOUE ,  Yuichiro Ajima ,  Shinya Hiramoto

IPC分类号： G06F15/76 ,  G06F9/06

CPC分类号： G06F15/17325

摘要： A synchronization apparatus includes a receiver that receives data from a synchronization apparatus of another node that performs synchronization with its own node from among the plurality of synchronization apparatuses and extracts synchronization information from the received data, a transmitter that transmits the data to the synchronization apparatus of the other node, a receiving state register that stores the extracted synchronization information, a delay unit that delays the received data by a specified period of time, and a controller that stores the extracted synchronization information and synchronization information from its own controller in the reception state register and causes the transmitter to transmit the data to the other node and returns the data to its own node back to its own controller via the delay unit when the extracted synchronization information and the synchronization information from its own controller are stored in the reception state register.

摘要翻译： 同步装置包括从多个同步装置中与其自身节点进行同步的另一节点的同步装置接收数据的接收机，从接收到的数据中提取同步信息的发送机，发送数据到同步装置的同步装置 另一个节点，存储所提取的同步信息的接收状态寄存器，将接收到的数据延迟指定时间段的延迟单元，以及将来自其自身的控制器的所提取的同步信息和同步信息存储在接收状态的控制器 注册并使得发送器将数据发送到另一个节点，并且当提取的同步信息和来自其自己的控制器的同步信息被存储在接收状态寄存器中时，经由延迟单元将数据返回到其自己的节点返回到其自己的控制器 。

公开(公告)号：US20100124241A1

公开(公告)日：2010-05-20

申请号：US12582119

申请日：2009-10-20

申请人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

发明人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

IPC分类号： H04J3/06

CPC分类号： G06F9/522 ,  G06F9/4843

摘要： A barrier synchronization apparatus includes a receiving device which transmits a first synchronization signal to a synchronization device when the first synchronization signal in which a transmission destination is set in advance according to setting conditions including an algorithm of the barrier synchronization and an execution condition is received. A synchronization device synchronizes n first synchronization signals which are set in advance according to the setting conditions, wherein n is a positive integer, and designates transmission of m second synchronization signals in which transmission destinations are set in advance according to the setting conditions after the synchronization is established, wherein m is a positive integer. A transmitting device transmits the second synchronization signals to m transmission destinations set in advance, when a transmission designation information indicating the transmission designation is received from the synchronization device.

摘要翻译： 屏障同步装置包括接收装置，当接收到根据包括屏障同步的算法和执行条件的设定条件，预先设定发送目的地的第一同步信号时，向同步装置发送第一同步信号。 同步装置根据设定条件同步预先设定的n个第一同步信号，其中n为正整数，并根据同步后的设定条件，指定发送目的地预先设定的m个第二同步信号的发送 其中m是正整数。 当从同步装置接收到指示发送指定的发送指定信息时，发送装置将第二同步信号发送到预先设定的m个发送目的地。

公开(公告)号：US08965996B2

公开(公告)日：2015-02-24

申请号：US13007288

申请日：2011-01-14

申请人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

发明人： Shinya Hiramoto ,  Yuichiro Ajima ,  Tomohiro Inoue

IPC分类号： G06F15/167 ,  G06F15/16 ,  G06F9/54 ,  H04L29/08

CPC分类号： G06F9/544 ,  H04L67/1097

摘要： A communication apparatus including: a receiving portion that receives alignment specifying information, the alignment specifying information indicating which of main memories included in a first information processing apparatus and a second information processing apparatus to align the requested data; a division location calculating portion that calculates a divisional location of the requested data so that the divisional location of the requested data becomes an alignment boundary on the main memory included in any one of the first and the second information processing apparatuses specified by the received alignment specifying information, the alignment boundary being integral multiples of a given data width; and a transmitting portion that divides the requested data stored into the main memory in the second information processing apparatus based on the calculated divisional location, and transmits the divided data to the first information processing apparatus.

摘要翻译： 一种通信装置，包括：接收对准指定信息的接收部分，指示包括在第一信息处理设备中的主存储器中的哪个存储器和对准所请求的数据的第二信息处理设备的对准指定信息; 分割位置计算部分，其计算所请求数据的分割位置，使得所请求数据的分割位置变为在由所接收的对准指定指定的第一和第二信息处理设备中的任一个中包括的主存储器上的对准边界 信息，对齐边界是给定数据宽度的整数倍; 以及发送部，其基于所计算的分割位置，将存储在第二信息处理装置中的主存储器中的请求数据分割，并将分割后的数据发送到第一信息处理装置。

公开(公告)号：US08725879B2

公开(公告)日：2014-05-13

申请号：US12699392

申请日：2010-02-03

申请人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

发明人： Yuichiro Ajima ,  Tomohiro Inoue ,  Shinya Hiramoto

IPC分类号： G06F15/16 ,  H04L29/08

CPC分类号： H04L67/14 ,  H04L67/142 ,  H04L69/161 ,  H04L69/162

摘要： A network interface device is provided. The network interface device is connected to a computer and performs communications via a network includes a first management unit that identifies a communication connection by a port number, and manages a communication connection state of each port by a context that is stored in a storage unit and is associated with a port number, a second management unit that manages a storage state of the context, and a control unit that refers to the context, and performs an exemplary operation to establish a communication connection and an exemplary operation to cut off a communication connection between ports.

摘要翻译： 提供网络接口设备。 网络接口设备连接到计算机并且经由网络执行通信包括通过端口号识别通信连接的第一管理单元，并且通过存储在存储单元中的上下文管理每个端口的通信连接状态，以及 与端口号相关联，管理上下文的存储状态的第二管理单元，以及参考上下文的控制单元，并且执行建立通信连接的示例性操作和用于切断通信连接的示例性操作 在端口之间。

公开(公告)号：US08572615B2

公开(公告)日：2013-10-29

申请号：US13325152

申请日：2011-12-14

申请人： Tomohiro Inoue ,  Yuichiro Ajima ,  Shinya Hiramoto

发明人： Tomohiro Inoue ,  Yuichiro Ajima ,  Shinya Hiramoto

IPC分类号： G06F9/46

CPC分类号： G06F15/17325 ,  G06F9/522

摘要： A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first and the second receiving state register.

摘要翻译： 同步装置包括从至少两个建立同步的同步装置接收数据的接收机，并从接收到的数据中提取同步信息和寄存器选择信息;向多个同步装置中的至少两个同步装置中的每一个发送数据的发送器， 的同步装置，分别存储所提取的同步信息的第一和第二接收状态寄存器，存储所提取的同步信息的第二接收状态寄存器，以及将所提取的同步信息存储到第一接收状态寄存器中的控制器， 基于寄存器选择信息交替地接收状态寄存器，并且当所提取的同步信息完成时，控制发送器将包括寄存器选择信息的数据发送到至少两个同步设备中的每一个 在第一和第二接收状态寄存器之一中。