摘要:
A communication apparatus including: a receiving portion that receives alignment specifying information, the alignment specifying information indicating which of main memories included in a first information processing apparatus and a second information processing apparatus to align the requested data; a division location calculating portion that calculates a divisional location of the requested data so that the divisional location of the requested data becomes an alignment boundary on the main memory included in any one of the first and the second information processing apparatuses specified by the received alignment specifying information, the alignment boundary being integral multiples of a given data width; and a transmitting portion that divides the requested data stored into the main memory in the second information processing apparatus based on the calculated divisional location, and transmits the divided data to the first information processing apparatus.
摘要:
A network interface device is provided. The network interface device is connected to a computer and performs communications via a network includes a first management unit that identifies a communication connection by a port number, and manages a communication connection state of each port by a context that is stored in a storage unit and is associated with a port number, a second management unit that manages a storage state of the context, and a control unit that refers to the context, and performs an exemplary operation to establish a communication connection and an exemplary operation to cut off a communication connection between ports.
摘要:
A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first and the second receiving state register.
摘要:
A reduction operation device detects a non-correspondence of an operation type or a data type in a reduction arithmetic operation of a parallel processing. The reduction operation device is inputted a plurality of the synchronization signals and data, sets each transmission destinations of the plurality of inputted synchronization signals and the plurality of data corresponding to a next stage of a reduction operation and executes the reduction operation. The synchronization unit in the reduction operation device detects the non-correspondence between the operation type or the data type included in an instruction of the reduction operation after the synchronization is established and controls the arithmetic operation of the arithmetic unit.
摘要:
A computer cluster arranged at a lattice point in a lattice-like interconnection network contains four nodes and an internal communication network. Two nodes can transmit packets to adjacent computer clusters located along the X direction, and the two other nodes can transmit packets to adjacent computer clusters located along the Y direction. Each node directly transmits a packet to an adjacent computer cluster in the direction in which the node can transmit packets, when the destination of the packet is located in the direction. When the destination of a packet to be transmitted from a node is not located in the direction in which the receiving node can transmit packets, the node transfers the packet to one of the other nodes through the internal communication network for transmitting the packet to the destination of the packet through the one of the other nodes.
摘要:
An I/O controller and method are provided. The I/O controller to which an I/O device can be connected, and instructs the I/O device to execute a process includes a descriptor transfer device that transfers a descriptor indicating contents of a process to be executed, and execution instruction unit that instructs the I/O device to execute the process, based on the descriptor transferred from the descriptor transfer device, wherein the descriptor transfer device includes a memory for storing the descriptor; descriptor reading unit that reads, according to an indication regarding a descriptor read source from a processor, an indicated descriptor from a main memory or said memory which stores the descriptor, and descriptor transfer unit that transfers the read descriptor to the execution instruction unit.
摘要:
A packet processing device for effectively assembling packets. A packet accumulator stores received packets. A packet analyzer extracts, from the packets, analysis information about flows to which the packets belong. A frequency predictor calculates a frequency prediction value based on the reception interval of packets belonging to an identical flow, and stores the calculated value in a frequency prediction storage. Also, in response to input of the analysis information, the frequency predictor reads the corresponding frequency prediction value and sends the read value to a flow processor. The flow processor generates flow information on the flow corresponding to the analysis information, and analyzes the generated flow information and those stored in a flow information storage, to select an assembling termination flow based on the frequency prediction values. A packet transfer unit reads the packets corresponding to the selected flow from the packet accumulator and transfers the packets to a host.
摘要:
A parallel computing system includes a plurality of processors multi-dimensionally commented by an interconnection network, wherein each of the processors in the parallel computing system determines, in dimensional order, communication channels to other processors in the interconnection network, each of the processors sets, as relative coordinates of destination processors with respect to the plurality of processors in data communications performed at a same timing, relative coordinates common to all of the processors, and each of the processors performs data communications with destination processors having the set relative coordinates.
摘要:
An information processing apparatus connected to another information apparatus in a parallel computer system via a plurality of routes, includes: an arithmetic processing device to issue an instruction for collection of congestion information and for communication; a route information holding unit to hold route information for performing communication; a transmission unit to transmit a congestion information collection packet to any of the plurality of routes; a reception unit to receive a congestion information collection response packet corresponding to the congestion information collection packet from any of the plurality of routes; and a control unit to cause the transmission unit to transmit a congestion information collection packet, to select route information from the route information holding unit based on congestion information included in the congestion information collection response packet, and to cause the transmission unit to perform communication instructed by the arithmetic processing device based on the selected route information.
摘要:
In a parallel computer system including a plurality of processors, processors are classified into a plurality of groups including a prescribed number of processors, and processors are connected to each other in a complete connecting manner in the groups. Those groups are connected to each other as the respective processors are connected in linear to each other.